• Journal of IKEEE
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• v.27 no.4
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• pp.573-578
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• 2023

This paper introduces a new locking technique applicable to high-performance digital Phase-Locked Loops (DPLL). The study employs additional thermometer codes to reduce quantization errors in LC-based Digital Controlled Oscillators (DCO). Despite not implementing the entire DCO codes in thermometer mode, this method effectively reduces quantization errors through enhanced linearity. In the initial locking phase, binary codes are used, and upon completion of locking, the system transitions to thermometer codes, achieving high frequency linearity and reduced jitter characteristics. This approach significantly reduces the number of switches required and minimizes the oscillator's area, especially in applications requiring low DCO gain (Kdco), compared to the traditional method that uses only thermometer codes. Furthermore, the jitter performance is maintained at a level equivalent to that of the thermometer-only approach. The efficacy of this technique has been validated through modeling and design at the RTL level using SystemVerilog and Verilog HDL.

• Journal of Sensor Science and Technology
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• v.26 no.1
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• pp.60-65
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• 2017

This paper describes the low noise and low power IC using the opamp sharing technique for the capacitive micro-sensor sensing platform. The proposed IC reduces noise using correlated double sampling (CDS) and reduces power consumption using the opamp sharing technique. The IC is designed to be fully programmable, and can be digitally controlled by serial peripheral interface (SPI). The power consumption and the integrated input referred noise are 1.02 mW from a 3.3 V supply voltage and $0.164aF_{RMS}$ with a bandwidth of 400 Hz. The capacitive sensitivity, the input-output linearity and the figure of merits (FoM) are 2.5 mV/fF, 2.46 %FSO, and 8.4, respectively.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2005.11a
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• pp.95-98
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• 2005

This paper presents intelligent digital redesign method of global approach for hybrid state space fuzzy-model-based controllers. For effectiveness and stabilization of continuous-time uncertain nonlinear systems under discrete-time controller, Takagi-Sugeno(TS) fuzzy model is used to represent the complex system. And global approach design problems viewed as a convex optimization problem that we minimize the error of the norm bounds between nonlinearly interpolated linear operators to be matched. Also by using the power series, we analyzed nonlinear system's uncertain parts more precisely. When a sampling period is sufficiently small, the conversion of a continuous-time structured uncertain nonlinear system to an equivalent discrete -time system have proper reason. Sufficiently conditions for the global state -matching of the digitally controlled system are formulated in terms of linear matrix inequalities (LMls). Finally, we prove the effectiveness and stabilization of the proposed intelligent digital redesign method by applying the chaotic Lorentz system.

• Proceedings of the KIEE Conference
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• 2011.07a
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• pp.1218-1219
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• 2011

본 논문은 KA555 Timer을 이용한 PWM회로로 구성된 아날로그 방식의 DC-DC Buck Converter와 AVR ATmega128를 이용한 PWM회로로 구성된 디지털 방식의 Buck Converter을 설계하여 각각의 특성을 비교 분석하였다. 제안된 컨버터들은 공통적으로 전원을 공급받아 전압분압회로를 통해 DC-DC Buck Converter의 PWM 제어회로부에 공급되며, 아날로그방식 컨버터의 제어부는 KA555 timer을 이용하여 구형파회로와 미분회로를 구성하고, 출력된 삼각파와 정현파를 KA555 timer을 이용하여 PWM파형으로 제어한다. 디지털방식의 컨버터는 AVR RISC 8-bit 마이크로프로세서 ATmega128을 이용하여 PWM 제어부를 구성하고 이를 LCD창을 통해 그 값을 확인할 수 있도록 설계하였다. 본 논문에서는 두 가지 방식의 제어부를 구성하여 제작 및 실험함으로써, 각각의 장단점을 비교하여 시스템 구성시 요구조건인 소형경량, 단가저감, 효율 등을 비교하여 그 상황에 맞는 설계가 가능할 것이다.

• Journal of Power Electronics
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• v.16 no.4
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• pp.1565-1577
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• 2016

For grid-connected LCL-filtered inverters, dual-loop current control with an inner-loop active damping (AD) based on capacitor current feedback is generally used for the sake of current quality. However, existing studies on capacitor current feedback AD with a control delay do not reveal the mathematical relation among the dual-loop stability, capacitor current feedback factor, delay time and LCL parameters. The robustness was not investigated through mathematical derivations. Thus, this paper aims to provide a systematic study of dual-loop current control in a digitally-controlled inverter. At first, the stable region of the inner-loop AD is derived. Then, the dual-loop stability and robustness are analyzed by mathematical derivations when the inner-loop AD is stable and unstable. Robust design principles for the inner-loop AD feedback factor and the outer-loop current controller are derived. Most importantly, ensuring the stability of the inner-loop AD is critical for achieving high robustness against a large grid impedance. Then, several improved approaches are proposed and synthesized. The limitations and benefits of all of the approaches are identified to help engineers apply capacitor current feedback AD in practice.

• Journal of Advanced Navigation Technology
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• v.18 no.3
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• pp.229-235
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• 2014

This paper presents the Doherty power amplifier with a digitally controlled analog predistorter circuit of Scintera Corp. to produce high power efficiency and high linearity performance. The analog predistorter improves the linearity performance because of controlling amplitude and phase values of input signal in order to improve intermodulation performance of power amplifier. Also, the power amplifier is designed by the Doherty technology to obtain the high efficiency performance. To validate the Scintera's analog predistorter, we are implemented the power amplifier with Doherty method at center frequency 2150 MHz. Compared with the balanced amplifier, the power amplifier is improved above 11% enhanced efficiency and more than 15 dB ACPR improvement.

• Proceedings of the Korea Concrete Institute Conference
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• 2006.05a
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• pp.98-101
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• 2006

As an alternative of conventional prestressed concrete (PSC) girders, various types of PSC girders are being developed and applied in bridge structures. Incrementally prestressed concrete girder is one of these newly developed girders. According to design concept, these new types of PSC girders have considerable advantages to reduce their self-weight and make spans longer. However, dynamic interaction between bridge superstructures and passing trains would be sometimes one of critical issues in these more flexible railway bridges. Therefore, it is very important to evaluate modal parameters of newly designed bridges before conducting dynamic analyses. In the present paper, a 25 meters long full scale PSC girder was fabricated as a test specimen and modal testing was carried out to evaluate modal parameters including natural frequencies and modal damping ratios at every prestressing stage. In the modal testing, a digitally controlled vibration exciter as well as an impact hammer is applied to obtain frequency response functions more exactly and the modal parameters are evaluated varying with construction stages. Prestressed force effects on changes of modal parameters are analyzed at every incremental prestressing stage.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.11
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• pp.79-85
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• 2004

A digitally-controlled analog-block inevitably undergoes the bang-bang oscillations which may cause a big amplitudes of the glitches if the oscillation occurs at the MSB transition points of a binary counter. The glitch results into the jitter noise for the case of the DLL. In this paper, we devise a new counter code that has the hysteresis in the bit transitions in order to prevent the transitions of the significant counter-bits at the locking state. The maximum clock jitter is simulated to considerably reduce over the voltage-temperature range guaranteed by specifications. The counter is employed to implement the high speed packet-base DRAM and contributes to the maximized valid data-window.

• ETRI Journal
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• v.38 no.3
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• pp.417-424
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• 2016

In this paper, an accurate characterization of a fabricated X-band transmit/receive module is described with the process of generating control data to correct amplitude and phase deviations in an active electronically scanned array antenna unit. In the characterization, quantization errors (from both a digitally controlled attenuator and a phase shifter) are considered using not theoretical values (due to discrete sets of amplitude and phase states) but measured values (of which implementation errors are a part). By using the presented procedure for the characterization, each initial control bit of both the attenuator and the phase shifter is closest to the required value for each array element position. In addition, each compensated control bit for the parasitic cross effect between amplitude and phase control is decided using the same procedure. Reduction of the peak sidelobe level of an array antenna is presented as an example to validate the proposed procedure.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.24 no.10 s.181
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• pp.2502-2512
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• 2000

Truss structures are widely used in many space structures, such as large antenna systems, space stations, precision segmented telescopes because they are light in weight and amenable in assembly or deployment. But, due to the low damping capacity, they remain excited for a long time once disturbed. These structural vibrations can reduce life of the structures and cause unstable dynamic characteristics. In this research, vibration suppression experiment has carried out with a three-dimensional 15-member truss structure using two piezoelectric actuators. Piezoelectric actuators which consist of stacks of thin piezoelectric material disks are directly inserted to the truss structure collocated with the strain sensors. Each actuator is controlled digitally in decentralized manner, based on local integral and proportional feedback. The optimal positions of the actuators are determined by the modal damping ratio and the control force. Numerical simulation has carried out to determine optimal position of each actuator.