• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• 한국항해항만학회 2005년도 춘계학술대회 논문집
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• pp.279-283
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• 2005

Fisheries Surveillance System (FSS) is to protect fishing farms a thief. To implement the FSS a speacial test system which can be operate at any natural environments in the practical farm fields is needed. This paper describes some up coming results for the implementation of Radar Car as the special test system which consists of small van-type car, commercial Radar system, Radar Scan Converter(RSC) and, computer system. This Radar Car is designed to test the influences of sea clutter according to the height of Radar Scanner and to verify some effects of side-lobe suppression by special materials attached at each side of the Radar scanner. The post digital signal processing of digital radar signal comes from Radar Scan Converter(RSC) is also discussed, then designed and developed a new RSC in this study.

• Nuclear Engineering and Technology
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• 제53권10호
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• pp.3406-3412
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• 2021

A real-time digital time-stamp sorting algorithm used in the In-Beam positron emission tomography (In-Beam PET) is presented. The algorithm is operated in the field programmable gate array (FPGA) and a small amount of registers, MUX and memory cells are used. It is developed for sorting the data of annihilation event from front-end circuits, so as to identify the coincidence events efficiently in a large amount of data. In the In-Beam PET, each annihilation event is detected by the detector array and digitized by the analog to digital converter (ADC) in Data Acquisition Unit (DAQU), with a resolution of 14 bits and sampling rate of 50 MS/s. Test and preliminary operation have been implemented, it can perform a sorting operation under the event count rate up to 1 MHz per channel, and support four channels in total, count rate up to 4 MHz. The performance of this algorithm has been verified by pulse generator and ²²Na radiation source, which can sort the events with chaotic order into chronological order completely. The application of this algorithm provides not only an efficient solution for selection of coincidence events, but also a design of electronic circuit with a small-scale structure.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권3호
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• pp.411-424
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• 2017

An all-digital delay-locked loop (DLL) for a mobile memory interface, which runs at 0.11-2.5 GHz with a phase-shift capability of $180^{\circ}$, has two internal DLLs: a global DLL which uses a time-to-digital converter to assist fast locking, and shuts down after locking to save power; and a local DLL which uses a phase detector with an adaptive phase sampling window (WPD) to reduce jitter accumulation. The WPD in the local DLL adjusts the width of its sampling window adaptively to control the loop bandwidth, thus reducing jitter induced by UP/DN dithering, input clock jitter, and supply/ground noise. Implemented in a 65 nm CMOS process, the DLL operates over 0.11-2.5 GHz. It locks within 6 clock cycles at 0.11 GHz, and within 17 clock cycles at 2.5 GHz. At 2.5 GHz, the integrated jitter is $954fs_{rms}$, and the long-term jitter is $2.33ps_{rms}/23.10ps_{pp}$. The ratio of the RMS jitter at the output to that at the input is about 1.17 at 2.5 GHz, when the sampling window of the WPD is being adjusted adaptively. The DLL consumes 1.77 mW/GHz and occupies $0.075mm^2$.

• Journal of the Institute of Electronics and Information Engineers
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• 제53권3호
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• pp.132-139
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• 2016

In the bandpass sampling(BPS), the sampling frequency for the analog-to-digital converter is lower than that of the signal to be sampled. Since the BPS operation results in the signal spectrum to be copied on the baseband, it is possible for the frequency down-converter to be conveniently omitted. The second-order BPS system is introduced in order to cancel the aliased interference components from the BPS output that may be generated by the BPS processing. In this paper, we introduce a design method for the optimal phase of the interpolant filter in the second-order BPS system which enables to maximally cancel the aliased components. Being mathematically derived, this method can always be applied independently to the spectral characteristics of the BPS input signal. The performance improvements by the suggested method has been measured statistically with various power spectra of the received signal, and it has been shown that the maximal amount of the improvements reaches up to 5~20 [dB] in comparison with the previous suboptimal algorithm.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• 제27권9호
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• pp.825-833
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• 2016

This paper introduces a direct-conversion CMOS RF transmitter for the IEEE 802.15.4 standard with a low-power high-gain up-conversion mixer designed in $0.18{\mu}m$ process. The designed RF DCT(Direct Conversion Transmitter) is composed of differential DAC(Digital to Analog Converter), passive low-pass filter, quadrature active mixer and drive amplifier. The most important characteristic in designing RF DCT is to satisfy the 2.4 GHz Zigbee standard in low power. The quadrature active mixer inside the proposed RF DCT provides enough high gain as well as sufficient linearity using a gain boosting technique. The measurement results for the proposed transmitter show very low power consumption of 7.8 mA, output power more than 0 dBm and ACPR (Adjacent Channel Power Ratio) of -30 dBc.

• Journal of the Korean Institute of Navigation
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• 제19권4호
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• pp.1-8
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• 1995

Although ship's draught information onboard is substantial for both the safety of navigation and the estimation of loaded cargoes, its accuracy depends, in conventional surveying method, on the skillfulness of observers and the condition of the sea surface round the vessel. To obtain more accurate information accessibly, measuring instruments with sophisticated sensors such as mechanical, electronic and ultrasonic transducers have been developed. However, they have still limitation in accuracy and in making up a system due to the complexity of processing signal. In this paper, we propose a new technique for analyzing ultrasonic pulse signal, in order to improve the measurement accuracy and simplify a remote sensing system of draught by ultrasonic waves. In this technique, pulse signal is translated into phase curve which is composed of the phase value defined in time domain. Then, the time interval between two signals different in waveform, is waveform, is analytically determined by calculating average time difference on phase curves. Also, analytical procedure can be carried out in real time with the successive five data sampled at T/4, for high speed digital processing with computer and A/D converter. This technique is useful for measuring draught under the influence of sea condition and for interfacing its data briefly to the integrated bridge system.

• Journal of Biosystems Engineering
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• 제13권2호
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• pp.28-37
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• 1988

This study was conducted to construct the soil bin system and associated microcomputer-based data acquisition system which is to be used for the effective evaluation of wheel performance. The soil bin system consists of four main parts; soil bin, carriage drive system, test carriage and soil processing carriage. The test carriage was constructed to measure the five performance parameters of testing wheels; pulling forte, motion resistance, sinkage and rotational speed of test wheel, and speed of test carriage. The test wheel is powered by a hydraulic system up to 8 ps. Soil processing carriage was designed to provide uniform test soil condition across the toil bin, and reproduction of soil conditions found satisfiable. The data acquisition system consists of APPLE II PLUS microcomputer, strain amplifier, I/O interface, A/D converter, digital counter and various transducers. It takes about 0.86 seconds to measure a set of performance parameters and store on the floppy disk simultaneously. Series of experiment showed that this system can be used effectively for evaluating the wheel performance associated with soil.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 한국해양정보통신학회 2001년도 추계종합학술대회
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• pp.307-310
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• 2001

In this paper we describe the design and implementation of uplink receiver for BWLL base station modem. The demodulator consists of digital down converter, matched filter and synchronization circuits. For symbol timing recovery we use Gardner algorithm. And we use forth power method and decision directed method for carrier frequency recovery and phase recovery, respectively. For the sake of performance analysis, we compare simulation results with the board implemented by FPGA which is APEX20KE series chip for Alter. The performance results show it works quite well up to the condition that a frequency offset equal to 4.7% of symbol rate.1

• ETRI Journal
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• 제33권6호
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• pp.897-903
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• 2011

A hybrid ${\Delta}{\Sigma}$ modulator for audio applications is presented in this paper. The pulse generator for digital-to-analog converter alleviates the requirement of the external clock jitter and calibrates the coefficient variation due to a process shift and temperature changes. The input resistor network in the first integrator offers a gain control function in a dB-linear fashion. Also, careful chopper stabilization implementation using return-to-zero scheme in the first continuous-time integrator minimizes both the influence of flicker noise and inflow noise due to chopping. The chip is implemented in a 0.13 ${\mu}m$ CMOS technology (I/O devices) and occupies an active area of 0.37 $mm^2$. The ${\Delta}{\Sigma}$ modulator achieves a dynamic range (A-weighted) of 97.8 dB and a peak signal-to-noise-plus-distortion ratio of 90.0 dB over an audio bandwidth of 20 kHz with a 4.4 mW power consumption from 3.3 V. Also, the gain of the modulator is controlled from -9.5 dB to 8.5 dB, and the performance of the modulator is maintained up to 5 nsRMS external clock jitter.

• IEIE Transactions on Smart Processing and Computing
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• 제4권4호
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• pp.258-264
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• 2015

The first 77 GHz transceiver that applies a heterodyne structure-based linear frequency modulation-frequency shift keying (LFM-FSK) front-end module (FEM) is presented. An LFM-FSK waveform generator is proposed for the transceiver design to avoid ghost target detection in a multi-target environment. This FEM consists of three parts: a frequency synthesizer, a 77 GHz up/down converter, and a baseband block. The purpose of the FEM is to make an appropriate beat frequency, which will be the key to solving problems in the digital signal processor (DSP). This paper mainly focuses on the most challenging tasks, including generating and conveying the correct transmission waveform in the 77 GHz frequency band to the DSP. A synthesizer test confirmed that the developed module for the signal generator of the LFM-FSK can produce an adequate transmission signal. Additionally, a loop back test confirmed that the output frequency of this module works well. This development will contribute to future progress in integrating a radar module for multi-target detection. By using the LFM-FSK waveform method, this radar transceiver is expected to provide multi-target detection, in contrast to the existing method.