• Journal of Broadcast Engineering
• /
• v.3 no.1
• /
• pp.69-84
• /
• 1998

In digital broadcasting, services such as digital satellite TV, cable TV and digital terrestrial TV, several video programs are compressed by MPEG-2, and then simultaneously transmitted over a conventional CBR (Constant Bit Rate) broadcasting channel. In this paper, we propose a joint quality control scheme to be able to accurately control the relative picture quality among the video programs, which is achieved by simdt;,nL'Ously controlling the video encoders to generate the VBR (Variable Bit Rate) compressed video streams. Our quality control scheme can prevent the video buffer overflow and underflow by total target bit allocation process, and also exactly control the relative picture quality in terms of PSNR (Peak Signal to Noise Ratio) between some programs requiring higher picture quality and others by rate-distortion modification. Furthermore we present a rate-distortion estimation method for MPEG-2 video, which is base of our joint quality control, and verify its performance by experiments. The most attractive features of this estimation method are as follows: 1) computational complexity is low because main operation for the estimation is to calculate the histogram of OCT coefficients into quantizer; 2) estimation results are very accurate enough to be applied to the practical MPEG-2 video coding applications. Simulation results show that the proposed joint quality control scheme accurately controls the relative picture quality among the video progran1s transmitted over a single channel as well as provides more consistent and higher picture quality than independent coding scheme that encodes each program independently.

• Journal of the Korean Society of Radiology
• /
• v.3 no.1
• /
• pp.11-15
• /
• 2009

In this study, the basic research verifying possibility of applications as radiology image sensor in Digital Radiography was performed, the radiology image sensor was fabricated using a multi-layer technique to decrease dark current. High efficiency materials in substitution for Amorphous Selenium(a-Se) have been studied as a direct method of imaging detector in Digital Radiography to decrease dark current by using PN junction or Hetero junction already used as solar cell, semiconductor. Particle-In -Binder method is used to fabricate radiology image sensor because it has a lot of advantages such as fabrication convenient, high yield, suitability for large area sensor. But high leakage current is one of main problem in Particle-In -Binder method. To make up for the weak points, multi-layer technique is used, and it is considered that high efficient digital radiation sensor can be fabricated with easy and convenient process. In this study, electrical properties such as leakage current, sensitivity, signal linearity is measured to evaluate multi-layer radiation sensor material.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.8 no.8
• /
• pp.1227-1234
• /
• 2013

An analog array with a 1.2 double poly floating gate transistor has been developed with a standard CMOS fabrication process. The programming of each cell by means of an efficient control circuit eliminates the unnecessary erasing operation which has been widely used in conventional analog memories. It is seen that the path of the signal for both the programming and the reading is almost exactly the same since just one comparator supports both operations. It helps to eliminate the effects of the amplifier input-offset voltage problem on the output voltage for the read operation. In the array, there is no pass transistor isolating a cell of interest from the adjacent cells in the array. Instead of the extra transistors, one extra bias voltage, Vmid, is employed. The experimental results from the memory shows that the resolution of the memory is equivalent to the information content of at least six digital cells. Programming/erasing of each cell is achieved with no detectable disturbance of adjacent cells. Finally, the unique shape of the injector structure in a EEPROM is adopted as a cell of analog array. It reduces the programming voltage below the transistor breakdown voltage without any special fabrication process.

• International Journal of Aeronautical and Space Sciences
• /
• v.17 no.4
• /
• pp.501-517
• /
• 2016

Synchronized switch damping (SSD) is a structural vibration control technique in which a piezoelectric patch attached to or embedded into the structure is connected to or disconnected from the shunt circuit in order to dissipate the vibration energy of the host structure. The switching process is performed by a digital signal processor (DSP) which detects the displacement extrema and generates a command to operate the switch in synchronous with the structure motion. Recently, autonomous SSD techniques have emerged in which the work of DSP is taken up by a low pass filter, thus making the whole system autonomous or self-powered. The control performance of the previous autonomous SSD techniques heavily relied on the electrical quality factor of the shunt circuit which limited their damping performance. Thus in order to reduce the influence of the electrical quality factor on the damping performance, a new autonomous SSD technique is proposed in this paper in which a negative capacitor is used along with the inductor in the shunt circuit. Only a negative capacitor could also be used instead of inductor but it caused saturation of negative capacitor in the absence of an inductor due to high current generated during the switching process. The presence of inductor in the shunt circuit of negative capacitor limits the amount of current supplied by the negative capacitance, thus improving the damping performance. In order to judge the control performance of proposed autonomous SSDNCI, a comparison is made between the autonomous SSDI, autonomous SSDNC and autonomous SSDNCI techniques for the control of an aluminum cantilever beam subjected to both single mode and multimode excitation. A value of negative capacitance slightly greater than the piezoelectric patch capacitance gave the optimum damping results. Experiment results confirmed the effectiveness of the proposed autonomous SSDNCI technique as compared to the previous techniques. Some limitations and drawbacks of the proposed technique are also discussed.

• Journal of Broadcast Engineering
• /
• v.6 no.2
• /
• pp.177-186
• /
• 2001

A digital watermark Is a perceptually unobtrusive signal embedded in some multimedia asset such as an Image for copyright protection. In many cases watermark detection amounts to thresholding a correlation vague between a watermark and a received image. Watermarking detection schemes can be classified into two types. Type 1 is based on a correlation process that is applied to the difference between an original image and an input Image to be tested. Type 2 is based on a correlation process that is directly applied to an input Image. The type 1 fails to prove the rightful ownership, while type 2 has an advantage in terms of rightful ownership compared with type 1. However, type 2 has a problem that doesnt appear in type 1. The problem is that correlation between a watermark and an original Image to be watermarked is trio significant to be ignored, when it Is normalized by watermarks energy. In this paper, based on the analysis of the correlation, we propose a novel watermarking scheme to minimize the effect and also verify the performance of the proposed scheme by experiments.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.51 no.9
• /
• pp.57-66
• /
• 2014

This paper presents a low-complexity barrel distortion correction processor for wide-angle cameras. The proposed processor performs the barrel distortion correction jointly with the color demosaicking, so that the hardware complexity can be reduced significantly. In addition, to reduce the required memory bandwidth, an efficient memory interface is proposed by utilizing the spatial locality of the memory access in the correction process. The proposed processor is implemented with 35K logic gates in a $0.11-{\mu}m$ CMOS process and its correction speed is 150 Mpixels/s at the operating frequency of 606MHz, where the supported frame size is $2048{\times}2048$ and the required memory bandwidth is 1 read/cycle.

• Journal of Broadcast Engineering
• /
• v.25 no.4
• /
• pp.587-597
• /
• 2020

In this paper, we analyze the normalization that occurs when processing digital hologram and propose an optimized quantization method. In JPEG Pleno, which standardizes the compression of holograms, full complex holograms are defined as complex numbers with 32-bit or 64-bit precision, and the range of values varies greatly depending on the method of hologram generation and object type. Such data with high precision and wide dynamic range are converted to fixed-point or integer numbers with lower precision for signal processing and compression. In addition, in order to reconstruct the hologram to the SLM (spatial light modulator), it is approximated with a precision of a value that can be expressed by the pixels of the SLM. This process can be refereed as a normalization process using quantization. In this paper, we introduce a method for normalizing high precision and wide range hologram using quantization technique and propose an optimized method.

• Journal of the Korean Society of Manufacturing Process Engineers
• /
• v.3 no.4
• /
• pp.73-80
• /
• 2004

A dual purpose robot automation system is developed for both arc welding and spot welding by one robot within a cell. The need for automation of both arc welding and spot welding processes is urgent while the production volume is not so big as to accommodate separate station for the two processes. Also, space is too narrow for separate station to be settled down in the factory. A spot welding robot is chosen and the function for arc welding are implemented in-house at cost of advanced functions. For the spot welding, a single pole type gun is used and the robot has to push down the plate to be welded, which causes the robot positioning error. Therefore, position error compensation algorithm is developed. The basic functions for the arc welding processes are implemented using the digital I/O board of robot controller, PLC, and A/D conversion PCB. The weaving pattern is taught in meticulously by manual teach. A fixture unit is also developed for dual purpose. The main aspects of the system is presented in this paper especially in the design and implementation procedure. The signal diagrams and sequence logic diagrams are also included. The outcome of the dual purpose welding cell is the increased productivity and good production stability which is indispensable for production volume prediction. Also, it leads to reduction of manufacturing lead time.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2008.10a
• /
• pp.463-466
• /
• 2008

With the development of Information Technology in recent years, the image has been an important means to store or express information. Generally, during the process of acquiring and storing images, the images can be corrupted by noise of which typical types are Impulse(Impulse Noise) and AWGN(Addiction White Gaussian Noise). Impulse noise shows irregularly in black and white over the length and breadth of the image by sharp and sudden disturbance of the image signal. In the Impulse noise environment, SM(Standard Median) filter would be used because of its good noise removal performance and simple algorithm. However, when SM filter removes noise, it also produces error at the edge of image and causes whole image quality deterioration. In this paper, we propose a method based on modified nonlinear filter operation scheme which enhances the features of noise removal and detail image preservation when restoring image in Impulse noise environment. And, we compared it with existing methods and the performances through simulation.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.35C no.10
• /
• pp.30-37
• /
• 1998

An analog array with a 1.2 $\mu\textrm{m}$ double poly floating gate transistor has been developed with a standard CMOS fabrication process. The programming of each cell by means of an efficient control circuit eliminates the unnecessary erasing operation which has been widely used in conventional analog memories. It is seen that the path of the signal for both the programming and the reading is almost exactly the same since just one comparator supports both operations. It helps to eliminate the effects of the amplifier input-offset voltage problem on the output voltage for the read operation. In the array, there is no pass transistor isolating a cell of interest from the adjacent cells in the array. Instead of the extra transistors, one extra bias voltage, Vmid, is employed. The experimental results from the memory shows that the resolution of the memory is equivalent to the information content of at least six digital cells. Programming/erasing of each cell is achieved with no detectable disturbance of adjacent cells. Finally, the unique shape of the injector structure in a EEPROM is adopted as a cell of analog array. It reduces the programming voltage below the transistor breakdown voltage without any special fabrication process.