• The Transactions of the Korean Institute of Electrical Engineers A
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• v.48 no.4
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• pp.461-466
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• 1999

A CMOS op amp with rail-to-rail input and output ranges is designed in a one-volt supply. The output stage of the op amp is used in a common source amplifier that operates in sub-threshold region to design a low voltage op amp with rail-to-tail output range. To drive heavy resistor and capacitor loads with rail-to-rail output ranges, a common source amplifier which has a low output resistance is utilized. A bulk-driven differential pair and a bulk-driven folded cascode amplifier are used in the designed op amp to increase input range and achieve 1 V operation. Post layout simulation results show that low frequency gain is about 58 ㏈ and gain bandwidth I MHz. The designed op amp has been fabricated in a 0.8${\mu}{\textrm}{m}$ standard CMOS process. The measured results show that this op amp provides rail-to-rail output range, 56㏈ dc gain with 1 MΩ load and has 0.4 MHz gain-bandwidth with 130 ㎊ and 1 kΩ loads.

• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.10
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• pp.1477-1483
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• 2013

This paper proposes a low-voltage current-mode integrator for a continuous-time current-mode baseband channel selection filter. The low-voltage current-mode linear cascode integrator is introduced to offer advantages of high current gain and improved unity-gain frequency. The proposed current-mode integrator has fully differential input and output structure consisting of CMOS complementary circuit. Additional cascode transistors which are operated in linear region are inserted for bias to achieve the low-voltage feature. Frequency range is also controllable by selecting proper bias voltage. From simulation results, it can be noticed that the implemented integrator achieves design specification such as low-voltage operation, current gain, and unity gain frequency.

• The KIPS Transactions:PartA
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• v.12A no.6 s.96
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• pp.531-538
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• 2005

In the high performance Analog Information Processing Systems(AIPS), gain boosting or additional gain stage is required when the gain is not sufficient with one stage amplification. This work shows that high gain is neatly obtained by enhancing the gain using the negative resistance element. Compared to the conventional techniques, the proposed scheme enjoys full output swing, small circuit area and power consumption, and the applications to various configurations of amplifiers. The negative resistance element is placed between the differential output nodes when used in the Op-Amp. The HSPICE simulation indicates that enhancement of more than 40 dB is readily obtained in this simple configuration when the negative resistance element is implemented in the form of cross-coupled CMOS inverters.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.3
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• pp.21-28
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• 2016

We propose an adaptive scheme of a differential codebook for temporally correlated channels. And the codeword entries of the propose codebook are selected among the set of M-PSK constellations - the values of M proposed in this paper are 8, 16, or 32. Firstly, we analyze mathematically how the optimal spherical cap radius of the proposed codebook is tracked. Then, we explain the practical implementation of the proposed adaptive method. Practically, some candidate differential codebooks we propose in this paper can be switched according to the temporal correlation coefficients of wireless channels in the proposed scheme. Monte-Carlo simulations demonstrate that the achievable throughput performance employing the proposed codebook is always superior to those of the differential codebooks employing M-PSK constellations and non-adaptive differential codebooks with the same amount of feedback information.

• Korean Journal of Optics and Photonics
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• v.11 no.2
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• pp.108-113
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• 2000

This paper presents a simple but novel gain deviation detector scheme which can be used for general gain-clamping systems. By using the difference of ASEJprobe powers extracted from the edges of gain-flattened bandwidth, gain deviation of EDFA can be exactly detected regardless of the operating condition of a constructed EDFA. To prove the vahd1ty of the suggested scheme, we Implemented gain clamping systems on a single EDFA and cascaded EDFA's link and achieved sufficient gam-clamping performance without the elaborate measurement for tlIe determination of control parameters. eters.

• Journal of the Korean Institute of Telematics and Electronics
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• v.4 no.4
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• pp.2-12
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• 1967

A pair of insulated-gate metal-oxide-semiconductor field-effect transistor has been used to measure the direct current produced from the ionization chamber in the range of to A. An analisis of direct-current differential amplifier giving the expressions of the common-mode rejection ratio and the rralization of the constant-current generator to give very large effective source resistance has been presented. Voltage gain is 6.6, drift at the room temperature is 1.5mv per day. The common-mode rejection ratio is obtained maximum 84db. These facts give the feasibility of small direct-current measurements by utilizing this type transistors.

• Journal of Communications and Networks
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• v.8 no.2
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• pp.205-211
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• 2006

This paper considers the maximum likelihood (ML) detection of 16-ary differential amplitude and phase shift keying (DAPSK) in Rayleigh fading channels. Based on the conditional likelihood function, two new receiver structures, namely ML symbol-by-symbol receiver and ML sequence receiver, are proposed. For the symbol-by-symbol detection, the conventional DAPSK detector is shown to be sub-optimum due to the complete separation in the phase and amplitude detection, but it results in very close performance to the ML detector provided that its circular amplitude decision thresholds are optimized. For the sequence detection, a simple Viterbi algorithm with only two states are adopted to provide an SNR gain around 1 dB on the amplitude bit detection compared with the conventional detector.

• Journal of the Korean Institute of Telematics and Electronics
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• v.19 no.1
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• pp.14-19
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• 1982

A differential amplifier has been designed and fabricated using aluminum-gate PMOS technology, Only enhaneement-mode MOSFET's are used in the circuit and the dimensions of transistors have been determined using simulation program MSINC. The fabricated integrated circuit with +15V and -l5V power supplies shows an open-loop DC voltage gain of 42 dB, a common mode rejection ratio (CMRR) of 50 dB, and a Power consumption of 20mW.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.4
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• pp.283-288
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• 2008

A post-linearization technique for the differrential CMOS LNA is presented. The proposed method uses an additional cross-coupled common-source FET pair to cancel out the third-order intermodulation ($IM_3$) current of the main differential amplifier. This technique is applied to enhance the linearity of CMOS LNA using $0.18-{\mu}m$ technology. The LNA achieved +10.2 dBm IIP3 with 13.7 dB gain and 1.68 dB NF at 2 GHz consuming 11.8 mA from a 1.8-V supply. It shows IIP3 improvement by 6.6 dB over the conventional cascode LNA without the linearizing circuit.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.65 no.12
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• pp.2177-2182
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• 2016

Using the existing exact but quite complicated symbol error rate (SER) expressions for M-ary phase shift keying (M-PSK) and M-ary differential phase shift keying (M-DPSK), we derive effective and concise closed-form asymptotic SER formulas especially in Rician-Nakagami fading channels. The derived formulas can be utilized to efficiently verify the achievable error rate performances of M-PSK and M-DPSK systems for the Rician-Nakagami fading environments. In addition, by exploiting the modulation gains directly obtained from the asymptotic SER formulas, we also theoretically demonstrate that M-DPSK suffers an asymptotic SER performance loss of 3.01dB with respect to M-PSK for a given M in Rician-Nakagami fading channels at high signal-to-noise ratio (SNR).