• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.8
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• pp.685-689
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• 2005

In the fabrication and design of MLCCs (Multilayer Ceramic Capacitors) with Ni inner electrode for medium and high voltage, reliability and dielectric breakdown mode have been investigated. For thickness of green sheet, the relationship between the rated voltage versus the thickness of green sheet. Increasing the thickness of green sheet increases the dielectric breakdown voltage. However, a practical limit to this linear relationship occurs at 30 urn and above. As the thickness of green sheet increased, dielectric breakdown voltage and weibull coefficient is increased, but abruptly decrease at 30 urn and 36 urn. When 24 urn of green sheet thickness, weibull coefficient and dielectric breakdown voltage were 13.58 and 70 V/um respectively. The results enabling the MLCCs to demonstrate high levels of reliability at medium and high voltage.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.6
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• pp.1128-1135
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• 2001

In this paper, a new HSG-Si formation technology, "seeding method', which employs Si$_2$H$_{6}$-molecule irradiation and annealing, was applied for realizing 64Mbit DRAMs. By using this technique, grain size controlled HSG-Si can be fabricated on in-situ phosphorous-doped amorphous-Si electrode. The new HSG-Si fabrication technology achieves twice the storage capacitance with high reliability for the stacked capacitors. In this technique, optimum process conditions of the phosphorous concentration, storage polysilicon deposition temperature and thickness of hemispherical grain silicon are in the range of 3.0-4.0E19atoms/㎤, 53$0^{\circ}C$ and 400$\AA$, respectively. In the 64M bit DRAM capacitor using optimum process conditions, limit thickness of dielectric nitride is about 65$\AA$.

• Proceedings of the Materials Research Society of Korea Conference
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• 2003.11a
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• pp.57-57
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• 2003

High dielectric constant materials (high K) have attracted a great deal of interest because of the dramatic scaling down of DRAM capacitor reaching its physical limit in terms of reduction of thickness. Among high-K materials that can replace silicon dioxide, tantalum pentoxide (Ta2O5) thin film, with their high dielectric constant (∼25) and good step coverage, is the candidate of choice.

• Journal of Electrical Engineering and Technology
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• v.12 no.2
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• pp.840-845
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• 2017

In this paper, in order to investigate the lifetime of oil-paper insulation, specimens were artificially aged with thermal and electrical multiple stresses. Accelerated ageing factors and equivalent operating years for each aging temperatures were derived from results of tensile strengths for the aged paper specimens. Also, the evaluation for the multi-stress aged specimens were carried out through the measurement of impulse breakdown voltage at high temperature of $85^{\circ}C$. The lifetimes of the oil-paper insulations were calculated with the value of 66.7 for 1.0 mm thickness specimens and 69.7 for 1.25 mm thickness specimens throughout the analysis of impulse BD voltages using equivalent operating years, which means that dielectric strengths would not be severely decreased until the mechanical lifetime limit. Therefore, for the lifetime evaluation of the oil-paper insulation, thermal aging would be considered as a dominant factor whereas electrical degradation would be less effective.

• Current Optics and Photonics
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• v.2 no.4
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• pp.378-382
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• 2018

In most previous investigations of plasmonic and metamaterial applications, the metallic film has been regarded as a perfect electrical conductor. Here we demonstrate the resonance characteristics of THz metamaterials fabricated from metal film that has a finite dielectric constant, using finite-difference time-domain simulations. We found strong redshift and spectral broadening of the resonance as we decrease the metal's plasma frequency in the Drude free-electron model. The frequency shift can be attributed to the effective thinning of the metal film, originating from the increase in penetration depth as the plasma frequency decreases. On the contrary, only peak broadening occurs with an increase in the scattering rate. The metal-thickness dependence confirms that the redshift and spectral broadening occur when the effective metal thickness drops below the skin-depth limit. The electromagnetic field distribution illustrates the reduced field enhancement and reduced funneling effects near the gap area in the case of low plasma frequency, which is associated with reduced charge density in the metal film.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.9
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• pp.29-35
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• 1992

Dielectric thin film of N/O (Si$_{3}N_[4}/SIO_{2}$) for high density stacked dynamic-RAM cell was formed by LPCVD and oxidation(Dry & pyrogenic oxidation methods) of the top Si$_{3}N_[4}$ film. The thickness, structure and composition of this film were measured by ellipsometer, high frequency C-V meter, high resolution TEM, AES, and SIMS. The thickness limit of Si$_{3}N_[4}$ film in making thin N/O structure layer was 7nm. In this experiment, the film with thinner than 7nm was not thick enough as oxygen diffusion barrier, and oxygen punched through the film and interfacial oxidation occurred at the phase boundary between Si$_{3}N_[4}$ and polycrystalline silicon electrode.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.11 no.1
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• pp.33-40
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• 1998

The composite SiO$_2$/Si$_3$N$_4$/SiO$_2$(ONO) film formed by oxidation on nitride film has been widely studied as DRAM stacked capacitor multi-dielectric films. Load lock(L/L) LPCVD system by HF cleaning is used to improve electrical capacitance and to scale down of effective thickness for memory device, but is brings a new problem. Nitride film deposited using HF cleaning shows selective deposition on poly silicon and oxide regions of capacitor. This problem is avoidable by carpeting chemical oxide using $H_2O$$_2$cleaning before nitride deposition. In this paper, we study the limit of nitride thickness for abnormal oxidation and the initial deposition time for nitride deposition dependent on underlayer materials. We proposed an advanced fabrication process for stacked capacitor in order to avoid selective deposition problem and show the usefulness of nitride deposition using L/L LPCVD system by $H_2O$$_2$cleaning. The natural oxide thickness on polysilicon monitor after HF and $H_2O$$_2$cleaning are measured 3~4$\AA$, respectively. Two substrate materials have the different initial nitride deposition times. The initial deposition time for polysilicon is nearly zero, but initial deposition time for oxide is about 60seconds. However the deposition rate is constant after initial deposition time. The limit of nitride thickness for abnormal oxidation under the HF and $H_2O$$_2$cleaning method are 60$\AA$, 48$\AA$, respectively. The results obtained in this study are useful for developing ultra thin nitride fabrication of ONO scaling and for avoiding abnormal oxidation in stacked capacitor application.

• Journal of the Korean Society for Precision Engineering
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• v.20 no.5
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• pp.218-224
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• 2003

This paper describes a novel MEMS integration technique on a CMOS chip. MEMS integration on CMOS circuit has many advantages in view of manufacturing cost and reliability. The surface topography of a CMOS chip from a commercial foundry has 0.9 ${\mu}{\textrm}{m}$ bumps due to the conformal coating on aluminum interconnect patterns, which are used for addressing each MEMS element individually. Therefore, it is necessary to achieve a flat mirror-like CMOS chip fer the microelectromechanical system (MEMS) such as micro mirror array. Such CMOS chip needs an additional thickness of the dielectric passivation layer to ease the subsequent planarization process. To overcome a temperature limit from the aluminum thermal degradation, this study uses RF sputtering of silicon nitride at low temperature and then polishes the CMOS chip together with the surrounding dummy pieces to define a polishing plane. Planarization reduces 0.9 ${\mu}{\textrm}{m}$ of the bumps to less than 25 nm.

• The Journal of the Korea institute of electronic communication sciences
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• v.12 no.5
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• pp.791-796
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• 2017

In this study, we investigated the influence of the fabrication process of stacked capacitors on the cell capacitance by using Load Lock (L/L) LPCVD system for dielectric thin film of DRAM capacitor. As a result, it was confirmed that the capacitance difference of about 3-4 fF is obtained by reducing the effective thickness of the oxide film by about $6{\AA}$ compared to the conventional non-L/L device. In addition, Cs was found to be about 3-6 fF lower than the calculated value, even though the measurement range of the thickness of the nitride film as an insulating film was in a normal management range. This is because the node poly FI CD is managed at the upper limit of the spec, resulting in a decrease in cell surface area, which indicates a Cs reduction of about 2fF. Therefore, it is necessary to control the thickness of insulating film and CD management within 10% of the spec center value in order to secure stable Cs.

• Journal of Navigation and Port Research
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• v.26 no.3
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• pp.289-294
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• 2002

The broadband high power 3-way combiner was designed and fabricated for the digital TV repeater. To achieve increase of the bandwidth and the high power capability, Wilkinson type power divider was adopted in our research. First of all, Wilkinson type power divider of equal-split and unequal-split were combined, and the characteristics of the four port in-phase power combiner was simulated for each thickness of dielectric substrates. As the results of simulation, the power combiner fabricated by using dielectric substrate of 120 mil-thickness has the characteristics as follows: insertion loss of less than -651 dB, reflection coefficient of less than -13 dB, isolation among the output ports of less than -15 dB, and pose difference among the output ports of smiler than 13$^{\circ}$. Therefore, this power combiner was possible to improve the limit of microstrip line width due to high impedance, the problem of power loss due to interaction between strip lines in a high power combiner and narrow bandwidth simultaneously. Furthermore, making broadband and high power could be achieved since the fabricated 3-way combiner has good characteristics of insertion loss, the reflection coefficient, separation between ports, and phase difference.