• 한국전기전자재료학회논문지
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• 제18권8호
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• pp.685-689
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• 2005

In the fabrication and design of MLCCs (Multilayer Ceramic Capacitors) with Ni inner electrode for medium and high voltage, reliability and dielectric breakdown mode have been investigated. For thickness of green sheet, the relationship between the rated voltage versus the thickness of green sheet. Increasing the thickness of green sheet increases the dielectric breakdown voltage. However, a practical limit to this linear relationship occurs at 30 urn and above. As the thickness of green sheet increased, dielectric breakdown voltage and weibull coefficient is increased, but abruptly decrease at 30 urn and 36 urn. When 24 urn of green sheet thickness, weibull coefficient and dielectric breakdown voltage were 13.58 and 70 V/um respectively. The results enabling the MLCCs to demonstrate high levels of reliability at medium and high voltage.

• 한국정보통신학회논문지
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• 제5권6호
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• pp.1128-1135
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• 2001

본 논문에서는 HSG형성을 위한 Si$_2$H$_{6}$의 조사와 어닐링을 통한 seeding method를 64Mbit DRAM에 적용하였다. 이 기술을 사용함으로서 인이 도우핑된 Amorphous 실리콘의 전극에 HSG grain 크기를 조절할 수 있었고, 이 새로운 HSG형성조건은 기존의 stack 캐패시터보다 약 2배의 정전용량을 확보할 수 있었다. 이와같은 방법을 이용한 HSG형성에서 인농도, 저장폴리 증착온도 및 HSG의 두께에 대한 공정 최적 조건으로는 각각 3.0-4.OE19atoms/㎤ , 53$0^{\circ}C$ 및 400$\AA$이었다. 이들 최적화된 공정조건으로 64M bit DRAM 캐패시터에 적용시 질화막의 두께 한계는 65$\AA$으로 확인되었다.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2003년도 추계학술발표강연 및 논문개요집
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• pp.57-57
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• 2003

High dielectric constant materials (high K) have attracted a great deal of interest because of the dramatic scaling down of DRAM capacitor reaching its physical limit in terms of reduction of thickness. Among high-K materials that can replace silicon dioxide, tantalum pentoxide (Ta2O5) thin film, with their high dielectric constant (∼25) and good step coverage, is the candidate of choice.

• Journal of Electrical Engineering and Technology
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• 제12권2호
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• pp.840-845
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• 2017

In this paper, in order to investigate the lifetime of oil-paper insulation, specimens were artificially aged with thermal and electrical multiple stresses. Accelerated ageing factors and equivalent operating years for each aging temperatures were derived from results of tensile strengths for the aged paper specimens. Also, the evaluation for the multi-stress aged specimens were carried out through the measurement of impulse breakdown voltage at high temperature of $85^{\circ}C$. The lifetimes of the oil-paper insulations were calculated with the value of 66.7 for 1.0 mm thickness specimens and 69.7 for 1.25 mm thickness specimens throughout the analysis of impulse BD voltages using equivalent operating years, which means that dielectric strengths would not be severely decreased until the mechanical lifetime limit. Therefore, for the lifetime evaluation of the oil-paper insulation, thermal aging would be considered as a dominant factor whereas electrical degradation would be less effective.

• Current Optics and Photonics
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• 제2권4호
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• pp.378-382
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• 2018

In most previous investigations of plasmonic and metamaterial applications, the metallic film has been regarded as a perfect electrical conductor. Here we demonstrate the resonance characteristics of THz metamaterials fabricated from metal film that has a finite dielectric constant, using finite-difference time-domain simulations. We found strong redshift and spectral broadening of the resonance as we decrease the metal's plasma frequency in the Drude free-electron model. The frequency shift can be attributed to the effective thinning of the metal film, originating from the increase in penetration depth as the plasma frequency decreases. On the contrary, only peak broadening occurs with an increase in the scattering rate. The metal-thickness dependence confirms that the redshift and spectral broadening occur when the effective metal thickness drops below the skin-depth limit. The electromagnetic field distribution illustrates the reduced field enhancement and reduced funneling effects near the gap area in the case of low plasma frequency, which is associated with reduced charge density in the metal film.

• 전자공학회논문지A
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• 제29A권9호
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• pp.29-35
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• 1992

Dielectric thin film of N/O (Si$_{3}N_[4}/SIO_{2}$) for high density stacked dynamic-RAM cell was formed by LPCVD and oxidation(Dry & pyrogenic oxidation methods) of the top Si$_{3}N_[4}$ film. The thickness, structure and composition of this film were measured by ellipsometer, high frequency C-V meter, high resolution TEM, AES, and SIMS. The thickness limit of Si$_{3}N_[4}$ film in making thin N/O structure layer was 7nm. In this experiment, the film with thinner than 7nm was not thick enough as oxygen diffusion barrier, and oxygen punched through the film and interfacial oxidation occurred at the phase boundary between Si$_{3}N_[4}$ and polycrystalline silicon electrode.

• 한국전기전자재료학회논문지
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• 제11권1호
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• pp.33-40
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• 1998

The composite SiO$_2$/Si$_3$N$_4$/SiO$_2$(ONO) film formed by oxidation on nitride film has been widely studied as DRAM stacked capacitor multi-dielectric films. Load lock(L/L) LPCVD system by HF cleaning is used to improve electrical capacitance and to scale down of effective thickness for memory device, but is brings a new problem. Nitride film deposited using HF cleaning shows selective deposition on poly silicon and oxide regions of capacitor. This problem is avoidable by carpeting chemical oxide using $H_2O$$_2$cleaning before nitride deposition. In this paper, we study the limit of nitride thickness for abnormal oxidation and the initial deposition time for nitride deposition dependent on underlayer materials. We proposed an advanced fabrication process for stacked capacitor in order to avoid selective deposition problem and show the usefulness of nitride deposition using L/L LPCVD system by $H_2O$$_2$cleaning. The natural oxide thickness on polysilicon monitor after HF and $H_2O$$_2$cleaning are measured 3~4$\AA$, respectively. Two substrate materials have the different initial nitride deposition times. The initial deposition time for polysilicon is nearly zero, but initial deposition time for oxide is about 60seconds. However the deposition rate is constant after initial deposition time. The limit of nitride thickness for abnormal oxidation under the HF and $H_2O$$_2$cleaning method are 60$\AA$, 48$\AA$, respectively. The results obtained in this study are useful for developing ultra thin nitride fabrication of ONO scaling and for avoiding abnormal oxidation in stacked capacitor application.

• 한국정밀공학회지
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• 제20권5호
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• pp.218-224
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• 2003

This paper describes a novel MEMS integration technique on a CMOS chip. MEMS integration on CMOS circuit has many advantages in view of manufacturing cost and reliability. The surface topography of a CMOS chip from a commercial foundry has 0.9 ${\mu}{\textrm}{m}$ bumps due to the conformal coating on aluminum interconnect patterns, which are used for addressing each MEMS element individually. Therefore, it is necessary to achieve a flat mirror-like CMOS chip fer the microelectromechanical system (MEMS) such as micro mirror array. Such CMOS chip needs an additional thickness of the dielectric passivation layer to ease the subsequent planarization process. To overcome a temperature limit from the aluminum thermal degradation, this study uses RF sputtering of silicon nitride at low temperature and then polishes the CMOS chip together with the surrounding dummy pieces to define a polishing plane. Planarization reduces 0.9 ${\mu}{\textrm}{m}$ of the bumps to less than 25 nm.

• 한국전자통신학회논문지
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• 제12권5호
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• pp.791-796
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• 2017

본 연구에서는 DRAM 커패시터의 유전막 박막화를 위한 Load Lock(L/L) LPCVD 시스템을 이용한 적층형 커패시터의 제조 공정이 셀 커패시턴스에 미치는 영향을 조사하였다. 그 결과 기존의 non-L/L 장치에 비하여 약 $6{\AA}$의 산화막 유효두께를 낮춤으로 커패시턴스로 환산 시 약 3-4 fF의 차이가 나타남을 확인할 수 있었다. 또한 절연막으로써 질화막 두께의 측정 범위가 정상적인 관리 범위의 분포임에도 불구하고 Cs는 계산치보다 약 3~6 fF 정도 낮은 것으로 확인되었다. 이는 node poly FI CD가 spec 상한치로 관리되어 셀 표면적의 감소를 초래하였고 이는 약 2fF의 Cs 저하를 나타내었다. 따라서 안정적인 Cs의 확보를 위해서는 절연막의 두께 및 CD 관리를 spec 중심값의 10 % 이내로 관리할 필요가 있음을 확인하였다.

• 한국항해항만학회지
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• 제26권3호
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• pp.289-294
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• 2002

본 논문에서는 디지털 TV 중계기용 고출력 광대역의 3-Way 전력결합기를 설계.제작하였다. 대역폭 증가와 고출력을 동시에 이루기 위하여 Wilkinson 형태의 전력분배기를 채택하였다. 우선 Wilkinson 전력분배기를 균등(1 : 1) 및 비균등(2 : 1) 분배시켜, 동위상 4 포트 전력결합기를 시뮬레이션 하였다. 시뮬레이션 결과에 따라서 두께 120 mil인 유전체 기판을 사용하여 제작된 전력결합기는 디지털 TV 중계기 주파수 470~806 MHz 대역에서 삽입손실 -6.53dB 이하, 반사계수 -13dB 이하, 포트 간 분리도 -15 dB 이하, 출력 포트 간 위상차가 13$^{\circ}$이하의 특성을 보였다. 새롭게 만든 전력결합기는 회로에서의 고 임피던스로 인한 마이크로스트립 선로 폭의 한계와 고출력의 경우 선로간의 상호작용으로 인한 전력의 손실 및 협대역의 문제를 동시에 개선이 가능함을 알 수 있었다. 나아가서, 제작된 3-Way 결합기의 삽입손실, 반사계수, 포트간의 분리도 및 위상차가 디지털 TV 중계주파수 470~806 MHz에서 양호한 특성을 나타내는 것을 확인함으로써 고출력 및 광대역화가 실현가능하다는 것을 알 수 있었다.