• 제목/요약/키워드: device degradation

검색결과 474건 처리시간 0.025초

인터페이스 회로와 디바이스 드라이버 통합 자동생성 시스템 설계 (Design of an Integrated Interface Circuit and Device Driver Generation System)

  • 황선영;김현철;이서훈
    • 한국통신학회논문지
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    • 제32권6B호
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    • pp.325-333
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    • 2007
  • 설계된 HW IP를 응용수준에서 제어하기 위해 OS상에서의 디바이스 드라이버가 요구된다. 디바이스 드라이버의 개발은 하드웨어와 OS에 대해 시스템 개발자의 정확한 이해가 필요하며 하드웨어 개발 기간과 비용의 많은 부분을 차지한다. 본 논문에서는 OS정보, 하드웨어 특징정보를 이용하여 OS에 따른 디바이스 드라이버를 인터페이스 회로와 함께 자동 생성하는 시스템의 구축에 대해 제시한다. 제안한 시스템에서는 효율적인 디바이스 드라이버 자동생성을 위해 디바이스 드라이버의 기본골격과 함수 모듈 코드, 헤더파일 테이블 등을 라이브러리로 구축하여 입력 데이터에 따라 선택되어 디바이스 드라이버가 자동생성 되도록 하였다. 제안된 방법으로 ARM922T 코어에 삼성 3.5인치 TFT-LCD를 장착하여 커널버전 ARM-Linux 2.4.19를 탑재한 후 디바이스 드라이버를 자동 생성하여 커널에 등록한 뒤 하드웨어에 write 연산을 실행하는데 걸린 시간을 비교한 결과 매뉴얼로 설계한 디바이스 드라이버에 비해 1.12%의 감소를 보였다. 커널 컴파일 후의 코드 사이즈는 0.17%의 증가를 보였다. 생성된 디바이스 드라이버는 응용프로그램 레벨에서 하드웨어를 제어할 때 발생하는 지연시간을 고려하면 실제 성능의 차이가 없음을 보인다. 본 논문에서 제안한 시스템을 사용하여 시스템 개발기간을 단축할 수 있다.

Submicron CMOSFET에서 기판 방향에 대한 소자 성능 의존성 분석

  • 박예지;한인식;박상욱;권혁민;복정득;박병석;이희덕
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2009년도 추계학술대회 논문집
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    • pp.7-7
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    • 2009
  • In this paper, we investigated the dependence of HCI (Hot Carrier Immunity) degradation and device performance on channel orientation in sub-micron PMOSFET. Although device performance ($I_{D.sat}$ vs. $I_{Off}$) was improved as the transistor angle increased HC immunity was degraded. Therefore, consideration of reliability characteristics as well as dc device performance is highly necessary in channel stress engineering of next generation CMOSFETs.

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유기 전기 luminescence 다이오드 특성 (A Characterization on Organic Electro-luminescence)

  • 이한성
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2007년도 학술대회 논문집 전문대학교육위원
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    • pp.165-169
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    • 2007
  • Organic EL has been expected to adopt to a new styles of technology that make flat display after Tang & Vanslyke made food electric luminescence device in late 1980s. Their studies based on multi layer structure that consists of emitting layer and carrier transporting layer using proper organic material. In this study we made multi layer device using $Eu(TTA)_3(phen)$ as a luminescence material by PVD and investigate luminous properties of each device. But oxidization of organic layer by ITO, energy walls in both pole interface, contaminations of ITO surface, importance of protecting membrane, diffusive dimming of light to cathode organic layer, these causes of degradations are common facts of a macromolecule and micromolecule. We think these degradation caused by the impact of heat and electro-chemical factor, bulk effect and interface phenomenon, and raise a question.

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Extreme baking effect of interlayer on PLED's performance

  • Kim, Mu-Gyeom;Kim, Sang-Yeol;Lee, Tae-Woo;Park, Sang-Hun;Park, Jong-Jin;Pu, Lyong-Sun
    • 한국정보디스플레이학회:학술대회논문집
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    • 한국정보디스플레이학회 2006년도 6th International Meeting on Information Display
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    • pp.1775-1778
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    • 2006
  • Through baking process on an interlayer, known as hole transporting layer, varying baking temperature up to 300 degree, which is considered as extremely high for polymer light emitting device (PLED) system, we found interesting relationship between packing density and morphology affecting device performance. Granular morphology shows that as temperature increases, grain size is getting smaller to pack closely and make interlayer harden. Such denser interlayer has temperature dependency of its own mobility, even without clear evidence of degradation of material itself. Its fact proven in a single film also reflects on multilayered PLED's performance like IVL, efficiency, lifetime. It's found that, especially, to enhance lifetime is related with thermal stability of interlayer and its mobility dependency to meet better charge balance. Therefore, it gives us understanding not only baking effect of interlayer, but also material & device designing guide to enhance lifetime.

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휴대용기기에 적합한 3차원 그래픽 렌더링 처리기의 파이프라인 설계 (The design of 3D graphics rendering processor for portable device)

  • 우현재;정종철;이문기
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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    • pp.1213-1216
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    • 2003
  • This paper proposes an 3D graphics rendering processor for portable device. One the most important factor is chip size for portable device, but the conventional 3D graphics rendering processor is not a suitable because the processor needs a lot of multiplication and division units. So the proposed architecture substitutes single precision floating point by 32 bit fixed point, and uses recursive units for the same operation such as color values(z, r, g, b, a) and texture values (s, t, u, v). In this approach, we reduce numbers of multiplications and divisions by 66.1% and 75% respectively at the sacrifice of performance degradation by 2.12%.

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초고속 구동을 위한 Ultra-thin Strained SGOI n-MOS 트랜지스터 제작 (High Performance nFET Operation of Strained-SOI MOSFETs Using Ultra-thin Strained Si/SiGe on Insulator(SGOI) Substrate)

  • 맹성렬;조원주;오지훈;임기주;장문규;박재근;심태헌;박경완;이성재
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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    • pp.1065-1068
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    • 2003
  • For the first time, high quality ultra-thin strained Si/SiGe on Insulator (SGOI) substrate with total SGOI thickness( $T_{Si}$ + $T_{SiGe}$) of 13 nm is developed to combine the device benefits of strained silicon and SOI. In the case of 6- 10 nm-thick top silicon, 100-110 % $I_{d,sat}$ and electron mobility increase are shown in long channel nFET devices. However, 20-30% reduction of $I_{d,sat}$ and electron mobility are observed with 3 nm top silicon for the same long channel device. These results clearly show that the FETs operates with higher performance due to the strain enhancement from the insertion of SiGe layer between the top silicon layer and the buried oxide(BOX) layer. The performance degradation of the extremely thin( 3 nm ) top Si device can be attributed to the scattering of the majority carriers at the interfaces.

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전류구동 능력 향상과 항복전압 감소를 줄이기 위한 새로운 비대칭 SOI 소자 (A New Asymmetric SOI Device Structure for High Current Drivability and Suppression of Degradation in Source-Drain Breakdown Voltage)

  • 이원석;송영두;정승주;고봉균;곽계달
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 1999년도 하계종합학술대회 논문집
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    • pp.918-921
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    • 1999
  • The breakdown voltage in fully depleted SOI N-MOSFET’s have been studied over a wide range of film thicknesses, channel doping, and channel lengths. An asynmmetric Source/Drain SOI technology is proposed, which having the advantages of Normal LDD SOI(Silicon-On-Insulator) for breakdown voltage and gives a high drivability of LDD SOI without sacrificings hot carrier immunity The two-dimensional simulations have been used to investigate the breakdown behavior in these device. It is found that the breakdown voltage(BVds) is almost same with high current drivability as that in Normal LDD SOI device structure.

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Study on the Improvement of Indirect Intra-Oral Dental Digital X-ray Image Sensor with Optical Coupling

  • Whang, Joo-Ho;Chung, Jin-Bum;Kim, Tae-Woo
    • Nuclear Engineering and Technology
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    • 제33권5호
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    • pp.514-525
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    • 2001
  • Optimum characteristics of digital X-ray sensor components were analyzed to develop intra- oral dental digital X-ray image sensor using indirect method. Parametric analysis was carried out to optimize the phosphor thickness and the fiber optic plate (FOP) coupling to charge coupled device (CCD). X-ray absorption and light diffusion in the phosphor layer were analyzed by the Monte Carlo method. Real time X-ray image was obtained with prototype X- ray image sensor using general CCD camera with 1∼10 Ip/mm resolution. It has been previously shown that large resolution degradation in X-ray images was caused by miss alignment of FOP to CCD and optical adhesive selection. In this study, we reported that X-ray image quality was greatly improved by using optimized characteristics of alignment device and phosphor thickness.

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격자온도 불균일 조건에서 SOI n-MOSFET의 전기적 특성 (Electrical properties of SOI n-MOSFET's under nonisothermal lattice temperature)

  • 김진양;박영준;민홍식
    • 전자공학회논문지A
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    • 제33A권3호
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    • pp.89-95
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    • 1996
  • In this ppaer, temeprature dependent transport and heat transport models have been incorperated to the two dimensional device simulator SNU-2D provides a solid bse for nonisothermal device simulation. As an example to study the nonisothermal problem. we consider SOI MOSFET's I-V characteristics have been simulated and compared with the measurements. It is shown that negative slopes in the Ids-Vds characteristics are casused by the temperature dependence of the saturation velocity and the degradation of the temperature dependence mobility. Also it is shown that the kink effect occurs when impact ionization near the drain produces a buildup of holes in this isolated device island, and the hysteresis is caused by the creation of holes in the channel and their flow to the source.

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유기 전기발광 소자에 관한 연구 (A Research on Organic Electro-luminescence)

  • 이한성
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2005년도 학술대회 논문집 전문대학교육위원
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    • pp.82-85
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    • 2005
  • Organic EL has been expected to adopt to a new styles of technology that make flat display after Tang & Vanslyke made good electric luminescence device in late 1980s. Their studies based on multi layer structure that consists of emitting layer and carrier transporting layer using proper organic material. In this study, we made multi layer device using $Eu(TTA)_3(phen)$ as a luminescence material by PVD and investigate luminous properties of each device. But oxidization of organic layer by ITO, energy walls in both pole interface, contaminations of ITO surface, importance of protecting membrane, diffusive dimming of light to cathode organic layer, these causes of degradations are common facts of a macromolecule and micromolecule. We think these degradation caused by the impact of heat and electro-chemical factor, bulk effect and interface phenomenon, and raise a question.

  • PDF