• Electrical & Electronic Materials
• /
• v.8 no.5
• /
• pp.619-625
• /
• 1995

Polycrystalline CdTe thin film has been studied for photovoltaic application due to the 1.45 eV band gap energy ideal for solar energy conversion and high absorption coefficient. The formation of low resistance contact to p-CdTe is difficult because of large work function(>5.5eV). Common methods for ohmic contact to p-CdTe are to form a p+ region under the contact by in-diffusion of contact material to reduce the barrier height and modify a p-CdTe surface layer using chemical treatment. In this study, the surface chemical treatment of p CdTe was carried out by H$\_$3/PO$\_$4/+HNO$\_$3/ or K$\_$2/Cr$\_$2/O$\_$7/+H$\_$2/SO$\_$4/ solution to provide a Te-rich surface. And various thin film contact materials such as Cu, Au, and Cu/Au were deposited by E-beam evaporation to form ohmic contact to p-CdTe. After the metallization, post annealing was performed by oven heat treatment at 150.deg. C or by RTA(Rapid Thermal Annealing) at 250-350.deg. C. Surface chemical treatments of p-CdTe thin film improved metal/p-CdTe interface properties and post heat treatment resulted in low contact resistivity to p-CdTe.Of the various contact metal, Cu/Au and Cu show low contact resistance after oven and RTA post-heat treatments, respectively.

• Transactions on Electrical and Electronic Materials
• /
• v.3 no.1
• /
• pp.30-37
• /
• 2002

A focusing grating coupler (FGC) was not fabricated by the 'Continuous Path Control'writing strategy but by an electron-beam lithography system of more general exposure mode, which matches not only the address grid with the grating period but also an integer multiple of the address grid resolution (5 nm). To more simplify the fabrication, we are able to reduce a process step without large decrease of pattern quality by excluding a conducting material or layer such as metal (Al, Cr, Au), which are deposited on top or bottom of an e-beam resist to prevent charge build-up during e-beam exposure. A grating pitch period and an aperture feature size of the FGC designed and fabricated by e-beam lithography and reactive ion etching were ranged over 384.3 nm to 448.2 nm, and 0.5 $\times$ 0.5 mm$^2$area, respectively. This fabrication method presented will reduce processing time and improve the grating quality by means of a consideration of the address grid resolution, grating direction, pitch size and shapes when exposing. Here our investigations concentrate on the design and efficient fabrication results of the FGC for coupling from slab waveguide to a spot in free space.

• Journal of the Korean GEO-environmental Society
• /
• v.9 no.4
• /
• pp.5-13
• /
• 2008

Just as infill material can reduce the shear strength of a rock joint, a layer of soft material between concrete and the surrounding rock socket can reduce pile shaft resistance of drilled shafts socketed in rocks. This can also result from construction methods that leave smeared or remoulded rock or drilling fluid residue on the sides of the rock sockets after concrete placement. The nature of the interface between the concrete pile shaft and the surrounding rock is critically important to the performance of the pile, and is heavily influenced by construction practice. Characteristics of the concrete-rock interface, such as roughness and the presence of the soft materials deposited during or after construction can significantly affect the shaft resistance response of the pile. In this study, we conducted the parametric study to examine the performance characteristics of drilled shafts socketed in smeared rock under the vertical load with the code of finite difference method of FLAC 2D. As the results of the current research, the parameters that affect the settlement of the pile head and the ultimate unit shaft resistance could be identified.

• Journal of the Korean Ceramic Society
• /
• v.43 no.11 s.294
• /
• pp.688-692
• /
• 2006

Ferroelectric lanthanides-substituted $Bi_4Ti_3O_{12}$ $(Bi_{4-x}Ln_xTi_3O_{12}, BLnT)$ thin films approximately 200 nm in thickness were deposited by metal organic chemical vapor deposition onto Pt(111)/Ti/SiO$_2$/Si(100) substrates. Many researchers reported that the lanthanides substitution for Bi in the pseudo-perovskite layer caused the distortion of TiO$_6$ octahedron in the a-b plane accompanied with a shift of the octahedron along the a-axis. In this study, the effect of lanthanides (Ln=Pr, Eu, Gd, Dy)-substitution and crystallization temperature on their ferroelectric properties of bismuth titanate $(Bi_4Ti_3O_{12}, BIT)$ thin films were investigated. As BLnT thin films were substituted to lanthanide elements (Pr, Eu, Gd, Dy) with a smaller ionic radius, the remnant polarization (2P$_r$) values had a tendency to increase and made an exception of the Eu-substituted case because $Bi_{4-x}Eu_xTi_3O_{12}$ (BET) thin films had the smaller grain sizes than the others. In this study, we confirmed that better ferroelectric properties can be expected for films composed of larger grains in bismuth layered peroskite materials. The crystallinity of the thin films was improved and the average grain size increased as the crystallization temperature,increased from 600 to 720$^{\circ}C$. Moreover, the BLnT thin film capacitor is characterized by well-saturated polarization-electric field (P-E) curves with an increase in annealing temperature. The BLnT thin films exhibited no significant degradation of switching charge for at least up to $1.0\times10^{11}$ switching cycles at a frequency of 1 MHz. From these results, we can suggest that the BLnT thin films are the suitable dielectric materials for ferroelectric random access memory applications.

• Journal of the Korean Ceramic Society
• /
• v.48 no.5
• /
• pp.479-484
• /
• 2011

In this paper, investigations of thick film $La_{0.75}Sr_{0.25}Ga_{0.8}Mg_{0.16}Fe_{0.04}O_{3-{\delta}}$ (LSGMF) cells fabricated via spin coating on either NiO-YSZ anode or $La_{0.7}Sr_{0.3}Ga_{0.6}Fe_{0.4}O_3$ (LSGF) cathode substrates are presented. A La-doped $CeO_2$ (LDC) layer is inserted between NiO-YSZ and LSGMF in order to prevent reactions from occurring during co-firing. For the LSGF cathode-supported cell, no interlayer was required because the components of the cathode are the same as those of LSGMF with the exception of Mg. An LSGMF electrolyte slurry was deposited homogeneously on the porous supports via spin coating. The current-voltage characteristics of the anode and cathode supported LSGMF cells at temperatures between $700^{\circ}C$ and $850^{\circ}C$ are described. The LSGF cathode supported cell demonstrates a theoretical OCV and a power density of ~420 mW $cm^2$ at $800^{\circ}C$, whereas the NiO-YSZ anode supported cell with the LDC interlayer demonstrates a maximum power density of ~350 mW $cm^2$ at $800^{\circ}C$, which decreased more rapidly than the cathode supported cell despite the presence of the LDC interlayer. Potential causes of the degradation at temperatures over $700^{\circ}C$ are also discussed.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.22 no.4
• /
• pp.664-669
• /
• 2018

To observe the relationship between the oxygen vacancy and electrical characteristics of $TiO_2$ due to the $CO_2$ gases, the $TiO_2$ were deposited by the mixing gases of $Ar:O_2=20$ sccm:20 sccm and annealed with various temperatures. The bonding structure was changed with the annealing temperature from amorphous to crystal structure, and the oxygen vacancy was also changed with these bonding structures. The $CO_2$ gas reaction of $TiO_2$ films showed the variation in accordance with the bonding structure. The capacitance increased at the amorphous structure $TiO_2$, and the current also increased. However the oxygen vacancy decreased at this amorphous structure $TiO_2$. Because of the formation of oxygen vacancies is in inverse proportion to the amorphous structure. Moreover, the diffusion current in the depletion layer such as the amorphous structure showed the difference in accordance with the $CO_2$ gas flow rates.

• Journal of the Korean institute of surface engineering
• /
• v.36 no.1
• /
• pp.14-21
• /
• 2003

Thin films of ZrO$_2$ and TiO$_2$ were deposited on Si(100) substrates using RF magnetron sputtering technique. To study an influence of the sputtering parameters, systematic experiments were carried out in this work. XRD data show that the $ZrO_2$ films were mainly grown in the [111] orientation at the annealing temperature between 800 and $1000^{\circ}C$ while the crystal growth direction was changed to be [012] at above $1000^{\circ}C$. FT-IR spectra show that the oxygen stretching peaks become strong due to $SiO_2$ layer formation between film layers and silicon surface after annealing, and proved that a diffusion caused by either oxygen atoms of $ZrO_2$ layers or air into the interface during annealing. Different crystal growth directions were observed with the various deposition parameters such as annealing temperature, RF power magnitude, and added $O_2$ amounts. The growth rate of $TiO_2$ thin films was increased with RF power magnitude up to 150 watt, and was then decreased due to a sputtering effect. The maximum growth rate observed at 150 watt was 1500 nm/hr. Highly oriented, crack-free, stoichiometric polycrystalline $TiO_2$<110> thin film with Rutile phase was obtained after annealing at $1000^{\circ}C$ for 1 hour.

• Journal of Sensor Science and Technology
• /
• v.14 no.2
• /
• pp.96-100
• /
• 2005

The planar Schottky diodes were fabricated and modeled to probe the device applicability of the cracked GaN epitaxial layer on a (111) silicon substrate. On the unintentionally n-doped GaN grown on silicon, we deposited Ti/Al/Ni/Au as the ohmic metal and Pt as the Schottky metal. The ohmic contact achieved a minimum contact resistivity of $5.51{\times}10.5{\Omega}{\cdot}cm^{2}$ after annealing in an $N_{2}$ ambient at $700^{\circ}C$ for 30 sec. The fabricated Schottky diode exhibited the barrier height of 0.7 eV and the ideality factor was 2.4, which are significantly lower than those parameters of crack free one. But in photoresponse measurement, the diode showed the peak responsivity of 0.097 A/W at 300 nm, the cutoff at 360 nm, and UV/visible rejection ratio of about $10^{2}$. The SPICE(Simulation Program with Integrated Circuit Emphasis) simulation with a proposed model, which was composed with one Pt/GaN diode and three parasitic diodes, showed good agreement with the experiment.

• Journal of Sensor Science and Technology
• /
• v.18 no.3
• /
• pp.239-244
• /
• 2009

We fabricated nano-templates by low temperature BCP(block copolymer) process at 180 $^{\circ}C$, then we deposited 10 nm-thick $TiO_2$ layers with ALD(atomic layer deposition) at low temperature of 150 $^{\circ}C$. Through FE-SEM analysis, we confirmed the successful formation of the groove-type(width of crest : 30 nm, width of trough : 18 nm) and the cylinder-type(diameter : 10 nm, distance between hole : 25 nm) templates. Moreover, after $TiO_2$-ALD processing, we confirmed the deposition of the uniform nano layers of $TiO_2$ on the nano-templates. Through AFM analysis, the pitches of the crest-through(in groove-type) and hole-hole(in cylinder-type) were the same before and after $TiO_2$-ALD processing. In addition, we indirectly determined the existence of the uniform $TiO_2$ layers on nano-templates as the surface roughness decreased drastically. We successfully fabricated nano-template at low temperature and confirmed that the three-dimensional nano-structure for sensor application could be achieved by $TiO_2$-ALD processing at extremely low temperature of 150 $^{\circ}C$.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.11 no.12
• /
• pp.1122-1127
• /
• 1998

Group II-AF_2$films such as $CaF_2$, $SrF_2$, and $BaF_2$ have been commonly used many practical applications such as silicon on insulatro(SOI), three-dimensional integrated circuits, buffer layers, and gate dielectrics in filed effect transistor. This paper presents electrical and structural properties of fluoride films as a gate dielectric layer. Conventional gate dielectric materials of TFTs like oxide group exhibited problems on high interface trap charge density($D_it$), and interface state incorporation with O-H bond created by mobile hydrogen and oxygen atoms. To overcome such problems in conventional gate insulators, we have investigated $CaF_2$ films on Si substrates. Fluoride films were deposited using a high vacuum evaporation method on the Si and glass substrate. $CaF_2$ films were preferentially grown in (200) plane direction at room temperature. We were able to achieve a minimum lattice mismatch of 0.74% between Si and $CaF_2$ films. Average roughness of $CaF_2$ films was decreased from 54.1 ${\AA}$ to 8.40 ${\AA}$ as temperature increased form RT and $300^{\circ}C$. Well fabricated MIM device showed breakdown electric field of 1.27 MV/cm and low leakage current of $10^{-10}$ A/$cm^2$. Interface trap charge density between $CaF_2$ film and Si substrate was as low as $1.8{\times}10^{11}cm^{-2}eV^{-1}$.