• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.10
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• pp.22-27
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• 1996

A digital logic demodulator for binary FSK signals is presented. The operation is based on the quadricorrelator which is known as an ideal frequency detector. The demodulator is especially suitable for high-speed application, and it can be easily implemented in integrated circuit. Computer simulation results show that the performance of the receiver with digital demodulator converges to that of analog quadricorrelator receiver as the number of mixing axes is increased and the optimum bandwidth depending on a modulation index is slightly wider than that of analog demodulator.

• Journal of Electrical Engineering and information Science
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• v.3 no.2
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• pp.139-144
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• 1998

This paper describes the design of a variable rate QPSK demodulator for digital satellite TV system. This true variable-rate demodulator employs a unique architecture to realize an all digital synchronization and detection algorithm. Data-flow based design approach enabled a seamless transition from high level design optimization to physical layout. The demodulator has been integrated with Viterbi decoder, de-interleaver, and Ree-Solomon decoder to make a single chip Digital Video Broadcast (DVB) receiver. The receiver IC has been fabricated with a 0.5mm CMOS TLM process and proved fully functional in a real-world set-up.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.249-252
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• 2001

The paper describes the physical design flow of QPSK Demodulator in operating 60MHz. It includes problems and issues of each design flow, verification process for physical layout.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.2
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• pp.194-200
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• 2003

In this paper, FSK(Frequency Shift Keying) demodulator which is widely used for FH-SS system is designed and the experimental results are analyzed. The performance of the ADPLL(All-digital Phase-Locked-Loop), which is the main part of the demodulator circuit, is analyzed by the computer program. Using Maxplus-II tool provided by altera. co., ltd, each part of the ADPLL is designed and all of them is integrated into EPM7064SLC44-10 chip. And the simulation results are compared with the characteristics of the implemented circuits for analysis. There is about 2${\mu}\textrm{s}$ difference in time constant of the PLL. This difference is not critical in the demodulator. And the experimental results show that the transmitted data is well demodulated when the phase difference between the FSK modulated signal and the reference signal is about 180 degree.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.10 no.1
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• pp.22-31
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• 1999

The conventional RZ-SSB demodulator consists of a limiter, FM demodulator and a linearizer. Since the conventional linearizer which cancels the high-order distortions must include Hilbert transformer, the performance of the demodulator are determined by the Hilbert transformer which is very complicated to realize in aeronautical telecommunication. This paper describes a method of designing RZ-SSB demodulator without Hilbert transformer. Since avionics systems are able to eliminate the inherent disadvantages in RZ-SSB, the results of this paper suggest that the RZ-SSB demodulator without Hilbert transformer is suitable for aeronautical telecommunication transceiver systems used in HF band.

• Proceedings of the IEEK Conference
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• 2000.11a
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• pp.81-84
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• 2000

This paper has been studied the design of 16-QAM demodulator used in broadband wireless local loop subscriber station. In B-WLL systems, transmission signal experience the inter symbol interference(ISI) due to multipath, frequency offset of RF/IF local oscillator and phase offset. In this paper, we discuss the effective data recovery algorithm for 16-QAM demodulator to compensate the distorted signal from ISI, frequency offset and phase offset.

• Proceedings of the IEEK Conference
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• 2007.07a
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• pp.129-130
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• 2007

I/Q demodulator is designed using RC-CR quadrature divider with two balanced mixer for WLAN applications. The I/Q demodulator has low power dissipation, good I/Q mismatch, a good isolation and conversion loss. The measured results shows close agreement with the predicted performance.

• Proceedings of the IEEK Conference
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• 2000.11a
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• pp.85-88
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• 2000

In order to resolve problems according to the phase error in QPSK demodulator of the digital communication systems. The demodulator requires carrier recovery loop which searches for the frequency and phase of the carrier. In this paper the complexity of implementation is reduced by the reduction into half of the number of the multiplier in filter structure of the conventional carrier recovery loop, and as the drawback of NCO of the conventional carrier recovery loop wastes a amount of power for the structure of lookup table , We designed the structure of combinational logic without the lookup table. In the comparison with dynamic power of the proposed NCO, the power of NCO with the lookup table is 175㎼, NCO with the proposed structure is 24.65㎼. As the result, it is recognized that about one eight of loss power is reduced. In the simulation of carrier recovery loop designed QPSK demodulator, it is known that the carrier phase is compensated.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.4
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• pp.256-261
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• 2011

We demonstrate 3-Gb/s wireless link using a 60-GHz receiver front-end fabricated in $0.25-{\mu}m$ SiGe:C bipolar complementary metal oxide semiconductor (BiCMOS) and a mixed-mode quadrature phase-shift keying (QPSK) demodulator fabricated in 60-nm CMOS. The 60-GHz receiver consists of a low-noise amplifier and a down-conversion mixer. It has the peak conversion gain of 16 dB at 62 GHz and the 3-dB intermediate-frequency bandwidth of 6 GHz. The demodulator using 1-bit sampling scheme can demodulate up to 4.8-Gb/s QPSK signals. We achieve successful transmission of 3-Gb/s data in 60 GHz through 2-m wireless link.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.8
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• pp.770-776
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• 2009

We propose and demonstrate an I/Q demodulator using four-port BPSK demodulator base on additive mixing and reflection-type phase shifter using hybrid technique. Previously, the conventional I/Q demodulator base on multiplicative or additive mixing method divides I/Q signal path from mixer to parallel-to-serial converter. In this paper, we propose new I/Q demodulator without dividing I/Q baseband signal path. The proposed schematic requires half size in implementation and half power consumption in baseband path compared with the conventional receiver. Also, the proposed receiver eliminates parallel-to-serial converter after data decoding. The proposed circuit has been successfully demodulated a QPSK signal with the L-band carrier frequency and 20 Mbps data rate.