JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
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3-Gb/s 60-GHz Link With SiGe BiCMOS Receiver Front-End and CMOS Mixed-Mode QPSK Demodulator

  • Received : 2011.10.27
  • Published : 2011.12.31
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Abstract

We demonstrate 3-Gb/s wireless link using a 60-GHz receiver front-end fabricated in $0.25-{\mu}m$ SiGe:C bipolar complementary metal oxide semiconductor (BiCMOS) and a mixed-mode quadrature phase-shift keying (QPSK) demodulator fabricated in 60-nm CMOS. The 60-GHz receiver consists of a low-noise amplifier and a down-conversion mixer. It has the peak conversion gain of 16 dB at 62 GHz and the 3-dB intermediate-frequency bandwidth of 6 GHz. The demodulator using 1-bit sampling scheme can demodulate up to 4.8-Gb/s QPSK signals. We achieve successful transmission of 3-Gb/s data in 60 GHz through 2-m wireless link.

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References

  1. A. M. Niknejad, "Siliconization of 60 GHz," IEEE Microwave Magazine, Vol.11, pp.78-85, Feb., 2010.
  2. IEEE 802.11ad Task Group.
  3. Wireless MAC and PHY Specifications for High Rate WPANs, IEEE Std. 802.15.3c, 2009.
  4. C. Marcu et al, "A 90 nm CMOS Low-Power 60 GHz Transceiver With Integrated Baseband Circuitry," Solid-State Circuits, IEEE Journal of, Vol.44, No.12, pp.3434-3447, Dec., 2009. https://doi.org/10.1109/JSSC.2009.2032584
  5. D. Kim et al, "Mixed-mode QPSK demodulator for home networking applications," Elelctonics Letters, Vol.47, No.2, pp.92-94, Jan., 2011. https://doi.org/10.1049/el.2010.2656
  6. D. Kim et al, "A 4.8-Gb/s Mixed-mode CMOS QPSK Demodulator for 60-GHz Wireless Personal Area Networks," Circuits and Systems, 2010, APCCAS 2010, IEEE Asia Pacific Conference on, 6-9, pp.60-63, Dec., 2010.
  7. M. Ko et al, "3-Gb/s Radio Link With SiGe BiCMOS 60-GHz Receiver Front-End," 11th RF Integrated Circuit Technology Workshop, 22-24, pp.549-550, Sep., 2011.
  8. B. Heinemann et al, "High-performance BiCMOS technologies without epitaxially-buried subcollectors and deep trenches," Semiconductor Science and Technology, Vol.22, No.1, pp.S153-157, Jan., 2007.
  9. T.-K. Nguyen et al, "CMOS Low-Noise Amplifier Design Optimization Techniques," Microwave Theory and Techniques, IEEE Transactions on, Vol.52, No.5, pp.1433-1442, May, 2004. https://doi.org/10.1109/TMTT.2004.827014
  10. T. Yao et al, "Algorithmic Design of CMOS LNAs and Pas for 60-GHz Radio," Solid-State Circuits, IEEE Journal of, Vol.42, No.5, pp.1044-1057, May, 2007. https://doi.org/10.1109/JSSC.2007.894325
  11. D. Kim et al, "A 622-Mb/s Mixed-Mode BPSK Demodulator Using a Half-Rate Bang-Bang Phase Detector," Solid-State Circuits, IEEE Journal of, Vol.43, No.10, pp.2284-2292, Oct., 2008. https://doi.org/10.1109/JSSC.2008.2004327