• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.9C
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• pp.581-588
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• 2011

In this paper, we propose a novel unambiguous code tracking scheme for cosine phased binary offset carrier (BOC) signals. We first obtain the sub-correlation functions composing the BOC autocorrelation function, and then, re-combine the sub-correlation functions generating a correlation function with no side-peak. Finally, by using the correlation function with no side-peak in the delay lock loop, the proposed scheme performs unambiguous signal tracking. Numerical results demonstrate that the proposed scheme provides a performance improvement over the conventional unambiguous scheme in terms of the tracking error standard deviation (TESD).

• The Proceeding of the Korean Institute of Electromagnetic Engineering and Science
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• v.5 no.4
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• pp.18-29
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• 1994

In this paper, the performance of stepped serial search scheme and matched filter scheme for code acqusition in FH / CDMA are evaluated under land mobile radio communication channel environments. And delay lock loop scheme is used as code tracking system. As the results for code acquisition system, it is shown that the performance of stepped searial scheme is superior to matched filter scheme, because system complexity is reduced and system performance is improved by increasing the hopping frequency not to substitute for special hardware. Also, it is shown that its performance is improved under Rayleigh/ Rician fading environments. As the results for code tracking system, it is found that mean hold time is increased due to the increase of the number of lock state and hopping frequency, M.

• Journal of IKEEE
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• v.22 no.4
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• pp.1158-1162
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• 2018

A fast-lock multiplying delay-locked loop (MDLL)-based digital clock frequency multiplier with an anti-harmonic lock capability is presented. The proposed digital frequency multiplier utilizes a new most-significant bit (MSB)-interval search algorithm to achieve fast-locking time without harmonic lock problems. The proposed digital MDLL frequency multiplier is designed in a 65nm CMOS process, and the operating output frequency range is from 1 GHz to 3 GHz. The digital MDLL provides a programmable fractional-ratio frequency multiplication ratios of N/M, where N = 1, 4, 5, 8, 10 and M = 1, 2, 3, respectively. The proposed MDLL consumes 3.52 mW at 1GHz and achieves a peak-to-peak (p-p) output clock jitter of 14.07 ps.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.2
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• pp.144-149
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• 2004

Register Controlled DLL with fast locking and low-power consumption, is described in this paper. Delay monitor scheme is proposed to achieve the fast locking and inverter is inserted in front of delay line to reduce the power consumption, also. Proposed DLL was fabricated in a 0.6${\mu}{\textrm}{m}$ 1-poly 3-metal CMOS technology. The proposed delay monitor scheme enables the DLL to lock to the external clock within 4 cycles. The power consumption is 36㎽ with 3V supply voltage at 34MHz clock frequency.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.1 no.1
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• pp.55-64
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• 1997

Spread Spectrum Communication is a core technique in CDMA system, but the problem for SS Communication schemes is synchronous method. There are DLL, Tau-dither, SO etc, in the synchronous method. But since there are analog operations, the settling is difficult and size is large. In this paper we realized Digital Delay Lock Loop (DDLL) and estimated it's performance through the Power line experiment.

• Proceedings of the IEEK Conference
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• 2000.06a
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• pp.209-212
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• 2000

In this paper, effect of imperfect power control on performance of a pseudonoise (PN) code tracking loop is analyzed and simulated for a direct-sequence/code-division multiple access (DS/CDMA) system. The multipath fading channel is modeled as a two-ray Rayleigh fading model. Power control error is modeled as a log-normally distributed random variable. The tracking performance of DLL (delay-locked-loop) is evaluated in terms of tracking jitter and mean-time-to-lose-lock (MTLL). From the simulation results, it is shown that the PN tracking performance is very sensitive to the power control error.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.11
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• pp.2378-2384
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• 2009

A novel phase-locked loop(PLL) architecture of sub-micron locking time has been proposed. Input frequency is multiplied by using a delay-locked loop(DLL). The input frequency of a PLL is multiplied while the PLL is out of lock. The multiplied input frequency makes the PLL having a wider loop bandwidth. It has been simulated with a $0.18{\mu}m$ 1.8V CMOS process. The simulated locking time is $0.9{\mu}s$ at 162.5MHz and 2.6GHz, input and output frequency, respectively.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.12C
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• pp.255-260
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• 2001

This paper describes the design of the Register Controlled DLL(Delay-Locked Loop) that achieves fast locking and low Power consumption using a new locking algorithm. A fashion for a fast locking speed is that controls the two controller in sequence. The up/down signal due to clock skew between a internal and a external clock in phase detector, first adjusts a large phase difference in coarse controller and then adjusts a small phase difference in fine controller. A way for a low power consumption is that only operates one controller at once. Moreover the proposed DLL shows better jitter performance Because using the lock indicator circuit. The proposed DLL circuit is operated from 50MHz to 200MHz by SPICE simulation. The estimated power dissipation is 15mA at 200MHz in 3.3V operation. The locking time is within 7 cycle at all of operating frequency.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 1998.11a
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• pp.243-247
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• 1998

SO(Synchronous Oscillator)는 동기, 동조, 필터, 증폭, 분주를 하나의 과정으로 처리할 수 있는 회로망이며, CPSO(Coherent Phase Synchronous Oscillator)는 50에 2개의 외부 루프를 첨가함으로서 구성되며, SO의 모든 장점을 유지하면서 동조범위 안에서 위상차가 없는 것이 큰 특징이다. 본 논문에서는 CPSO의 이러한 성질을 이용하여 GPS (Global Positioning System)에서 많이 사용하고 있는 부호동기방식인 DLL(Delay Lock Loop)과 TDL(Tau dither Loop)을 대치할 수 있는, 회로가 간단하고 추적범위가 넓으며 동기가 용이한 CPSO를 GPS의 부호동기 시스템에 적용하였다.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1984.10a
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• pp.43-47
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• 1984

This paper describes the mean time delay and its variance before transition from search to lock mode by means of signal flow graph and its transfer function. A relation between hit probability and search stage number is presented with the comparison of the open loop and closed loop. From these results optimum transition probability which we must hold can be obtained.