• Title/Summary/Keyword: decoder circuit

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Design of Reed Solomon Decoder for Optical Disks (광학식 디스크를 위한 Reed Solomon 복호기 설계)

  • 김창훈;박성모
    • Proceedings of the IEEK Conference
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    • 2000.06b
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    • pp.262-265
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    • 2000
  • This paper describes design of a (32, 28) Reed Solomon decoder for optical compact disk provides double error detecting and correcting capability. The most complex circuit in the RS decoder is part for solving the error location numbers from error location polynomial, and the circuit has great influence on overall decoder complexity. We use RAM based architecture with Euclid algorithm, Chien search algorithm and Forney algorithm. We have developed VHDL model and Performed logic synthesis using the SYNOPSYS CAD tool. Then, the RS decoder has been implemented with FPGA. The total umber of gate is about 11,000 gates and it operates at 20MHz.

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Analog Parallel Processing-based Viterbi Decoder using Average circuit (Average 출력회로를 이용한 아날로그 병렬처리 기반 비터비 디코더)

  • Kim, Hyung-Jung;Kim, In-Cheol;Kim, Hyong-Suk
    • Proceedings of the KIEE Conference
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    • 2006.10c
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    • pp.375-377
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    • 2006
  • A Analog parallel processing-based Viterbi decoder which decodes PRML signal of DVD has been designed by CMOS circuit. The analog processing-based Viterbi decoder implements are functions of the conventional digital Viterbi decoder utilizing the analog parallel processing circuit technology. The Analog parallel processing-based Viterbi decoding technology is applied for the PR(1,2,2,1) signal decoding of DVD. The benefits are low power consumption and less silicon consumption. In this paper, the comparison of the Analog parallel processing-based Viterbi Decoder which has a function of the error correction between Max operation and Average operation is discussed.

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Design of High-performance Viterbi Decoder Circuit by Efficient Management of Path Metric Data (경로 메트릭 데이터의 효율적인 관리를 통한 고성능 비터비 디코더 회로 설계)

  • Kim, Soo-Jin;Cho, Kyeong-Soon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.47 no.7
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    • pp.44-51
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    • 2010
  • This paper proposes the architecture of high-performance Viterbi decoder circuit. The proposed circuit does not require additional memory to calculate the branch metrics because it uses the characteristics of the branch data. The speed of the Viterbi decoder circuit is increased up to 75% by rearranging the path metric data in SRAM and registers properly for fast add-compare-select operations. We described the proposed Viterbi decoder circuit in Verilog HDL and synthesized the gate-level circuit using 130nm standard cell library. The synthesized circuit consists of 8,858 gates and its maximum operating frequency is 130MHz.

Improvement of Time-Delay of the Analog Viterbi Decoder through Minimizing Parasitic Capacitors in Layout Design (아날로그 비터비 디코더에 있어서 기생 cap성분 최소화 layout 설계에 의한 신호전파 지연 개선)

  • Kim, In-Cheol;Kim, Hyun-Jung;Kim, Hyong-Suk
    • Proceedings of the KIEE Conference
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    • 2007.04a
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    • pp.196-198
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    • 2007
  • A circuit design technique to reduce the propagation time is proposed for the analog parallel processing-based Viterbi decoder. The analog Viterbi decoder implements the function of the conventional digital Viterbi decoder utilizing the analog parallel processing circuit technology. The decoder is for the PR(1.2,2.1) signal of DVD. The benefits are low power consumption and less silicon occupation. In this paper, a propagation time reduction technique is proposed by minimizing the parasitic capacitance components in the layout design of the analog Viterbi decoder. The propagation time reduction effect of the proposed technique has been shown via HSPICE simulation.

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Parallel Decoder Module for Digital-Information Translation of Optical Disc (광디스크 디지털 정보 전송을 위한 병렬구조 디코더 모듈)

  • Kim, Jong-Man;Kim, Yeong-Min;Shin, Dong-Yong;Seo, Bum-Su
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2010.06a
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    • pp.289-289
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    • 2010
  • Translation Characteristics of Digital Decoder utilizing the analog parallel processing circuit technology is designed. The fast parallel viterbi decoder system acted by a replacement of the conventional digital viterbi Decoder has good propagation. we are applied proposed analog viterbi decoder to decode PR signal for DVD and analyze the specific circuit and signal characteristics.

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Design and Fabrication of a Seven Segment Decoder/Driver with PMOS Technology (PMOS 집적회로 제작기법을 사용한 Seven Segment Decoder/Driver의 설계와 제작)

  • 김충기;박형규
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.15 no.3
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    • pp.11-17
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    • 1978
  • A medium scale integrated circuit, BCD to seven segment decoder/driver is designed and fabricated by employing P-channel metal-oxide-semiconductor technology. The device configuration is specifically designed for a common cathode seven segment LED display unit. The decoder logic is composed of two serially connected read-only-memory matrices and the LED drivers are implemented with wide channel FET's. The fabricated integrated circuit performed successfully with a supply voltage between -7 Volt and -26 Volt and the non-uniformity of the LED segment current is about 10%.

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Design Optimization of the Arithmatic Logic Unit Circuit for the Processor to Determine the Number of Errors in the Reed Solomon Decoder (리드솔로몬 복호기에서 오류갯수를 계산하는 처리기의 산술논리연산장치 회로 최적화설계)

  • An, Hyeong-Keon
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.36 no.11C
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    • pp.649-654
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    • 2011
  • In this paper, we show new method to find number of errors in the Reed-Solomon decoder. New design is much faster and has much simpler logic circuit than the former design method. This optimization was possible by very simplified square calculating circuit and parallel processing. The microcontroller of this Reed Solomon decoder can be used for data protection of almost all digital communication and consumer electronic devices.

VLSI Design of 3-Bit Soft Decision Viterbi Decoder (3-Bit Soft Decision Viterbi 복호기의 VLSI 설계)

  • 김기명;송인채
    • Proceedings of the IEEK Conference
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    • 1999.11a
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    • pp.863-866
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    • 1999
  • In this paper, we designed a Viterbi decoder with constraint length K=7, code rate R=1/2, encoder generator polynomial (171, 133)$_{8}$. This decoder makes use of 3-bit soft decision. We designed the Viterbi decoder using VHDL. We employed conventional logic circuit instead of ROM for branch metric units(BMUs) to reduce the number of gates. We adopted fully parallel structures for add-compare-select units(ACSUs). The size of the designed decoder is about 200, 000 gates.s.

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Design of Multiple Valued Logic Circuits with ROM Type using Current Mode CMOS (전류방식 CMOS에 의한 ROM 형의 다치 논리 회로 설계)

  • 최재석;성현경
    • Journal of the Korean Institute of Telematics and Electronics B
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    • v.31B no.4
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    • pp.55-61
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    • 1994
  • The multiple valued logic(MVL) circuit with ROM type using current mode CMOS is presented in this paper. This circuit is composed of the multiple valued-to-binary(MV/B) decoder and the selection circuit. The MV/B decoder decodes the single input multiple valued signal to N binary signal, and the selection circuits is composed N$\times$N array of the selecion cells with ROM types. The selection cell is realized with the current mirror circuits and the inhibit circuits. The presented circuit is suitable for designing the circuit of MVL functions with independent variables, and reduces the number of selection cells for designing the circuit of symmetric MVL functions as many as {($N^2$-N)/2}+N. This circuit possess features of simplicity. expansibility for array and regularity, modularity for the wire routing. Also, it is suitable for VLSI implementation.

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Optimizing the Circuit for Finding 2 Error Positions of 2 Error Correcting Reed Solomon Decoder (리드솔로몬 복호기에서 2개의 오류시, 오류위치를 찾는 최적화 방법)

  • An, Hyeong-Keon
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.36 no.1C
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    • pp.8-13
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    • 2011
  • In this paper, we show new method to find error locations of 2 eight bit symbol errors for 2 error correcting Reed-Solomon decoder. New design is much faster and has much simpler logic circuit than the former design method. This optimization was possible by partitioning the 8 bit operations into 4 bit arithgmatic and logic operations. This Reed Solomon decoder can be used for data protection of almost all digital communication and consumer electronic devices.