Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Design of High-performance Viterbi Decoder Circuit by Efficient Management of Path Metric Data

경로 메트릭 데이터의 효율적인 관리를 통한 고성능 비터비 디코더 회로 설계

  • Kim, Soo-Jin (Department of Electronics Engineering, Hankuk University of Foreign Studies) ;
  • Cho, Kyeong-Soon (Department of Electronics Engineering, Hankuk University of Foreign Studies)
  • 김수진 (한국외국어대학교 전자공학과) ;
  • 조경순 (한국외국어대학교 전자공학과)
  • Received : 2009.10.17
  • Accepted : 2010.06.15
  • Published : 2010.07.25
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Abstract

This paper proposes the architecture of high-performance Viterbi decoder circuit. The proposed circuit does not require additional memory to calculate the branch metrics because it uses the characteristics of the branch data. The speed of the Viterbi decoder circuit is increased up to 75% by rearranging the path metric data in SRAM and registers properly for fast add-compare-select operations. We described the proposed Viterbi decoder circuit in Verilog HDL and synthesized the gate-level circuit using 130nm standard cell library. The synthesized circuit consists of 8,858 gates and its maximum operating frequency is 130MHz.

본 논문은 고성능 비터비 디코더 회로 구조를 제안한다. 제안하는 비터비 디코더는 가지 값의 특징을 이용하기 때문에 추가적인 메모리를 사용하지 않고 가지 메트릭을 계산할 수 있다. 또한 빠른 합-비교-선택 연산을 위해 경로 메트릭 데이터를 SRAM과 레지스터에 적절하게 재배열함으로써 디코더 전체의 속도를 75%까지 향상시킨다. 제안하는 비터비 디코더 회로를 Verilog HDL로 설계하였으며 130nm 표준 셀 라이브러리를 이용하여 게이트 수준 회로로 합성하였다. 제안하는 회로는 8,858개의 게이트로 구성되며 회로의 최대 동작 주파수는 130MHz이다.

Keywords

Acknowledgement

Grant : 차세대 광통신용 다지털 신호처리 기반 초고속 CMOS회로 설계 기술

Supported by : 한국산업기술평가관리원, 한국외국어대학교

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