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http://dx.doi.org/10.7840/KICS.2011.36C.1.8

Optimizing the Circuit for Finding 2 Error Positions of 2 Error Correcting Reed Solomon Decoder  

An, Hyeong-Keon (동명대학교 정보통신공학과)
Publication Information
The Journal of Korean Institute of Communications and Information Sciences / v.36, no.1C, 2011 , pp. 8-13 More about this Journal
Abstract
In this paper, we show new method to find error locations of 2 eight bit symbol errors for 2 error correcting Reed-Solomon decoder. New design is much faster and has much simpler logic circuit than the former design method. This optimization was possible by partitioning the 8 bit operations into 4 bit arithgmatic and logic operations. This Reed Solomon decoder can be used for data protection of almost all digital communication and consumer electronic devices.
Keywords
Reed-Solomon(RS); Decoder; GF($2^4$); Communication; Digital; Error location; Symbol; GF($2^8$);
Citations & Related Records
Times Cited By KSCI : 3  (Citation Analysis)
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