• JSTS:Journal of Semiconductor Technology and Science
• /
• v.11 no.4
• /
• pp.336-343
• /
• 2011

This paper introduces a simple variable gain amplifier (VGA) structure that shows an inherently dB-linear gain control property. Requiring no additional components for dB-linear control, the structure is compact and power efficient. The designed two-stage VGA shows a gain control range of 60dB with the gain error in the range of ${\pm}0.4$ dB. The power consumption including the output buffer is 20.4 mW from 1.2 V supply voltage with bandwidth of 630 MHz. The prototype was fabricated in a 0.13 ${\mu}m$ CMOS process and the VGA core occupies 0.06 $mm^2$.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.48 no.7
• /
• pp.23-29
• /
• 2011

A dB-linearity improved variable gain amplifier (VGA) for GPS receiver is presented. The Proposed dB-linear current generator has improved dB-linearity error of ${\pm}0.15$dB. The VGA for GPS is designed using proposed dB-linear current generator and composed of 3 stage amplifiers. The IF frequency is assumed as 4MHz and the linearity requirement of the VGA for GPS receiver is defined as 24dBm of IIP3 using cascaded IIP3 equation and the VGA satisfies 24dBm when minimum gain mode. The DC-offset voltage is eliminated using DC-offset cancelation loop. The gain range is from -8dB to 52dB and the dB-linearity error satisfies ${\pm}0.2$dB. The 3-dB frequency has range of 35MHz~106MHz for the gain range. The VGA is designed using 0.18${\mu}m$ CMOS process. The power consumption is 3mW with 1.8V supply voltage.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.44 no.8
• /
• pp.16-21
• /
• 2007

CMOS variable gain amplifier (VGA) IC designs for the structure monitoring systems of the telemetries were developed. A three stage cascaded VGA using a differential amplifier and a linear-in-dB controller is presented. A proposed VGA is a modified version of a conventional VGA such that the gain is controlled in a linear-in-dB fashion through the current ratio. The proposed VGA circuit introduced in this paper has a dynamic range of 77 dB with 1.5 dB gain steps. It also achieved a gain error of less than 1.5 dB over 77 dB gain range. The VGA can operate up to 10MHz dissipating 13.8 mW from a single 1.8 V supply. The core area of the VGA fabricated in a Magnachip $0.18{\mu}m$ standard CMOS process was about $430{\mu}m{\times}350{\mu}m$. According to measurement results, we can verify that the proposed method is reasonable with regard to the enhancement of dynamic range and the better linear-in-dB characteristics.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.14 no.5
• /
• pp.579-587
• /
• 2014

This paper presents a variable gain amplifier (VGA) for an analog front-end (AFE) of ultrasound medical imaging. This VGA has a closed-loop topology and shows a 37-dB-linear characteristic with a single-stage amplifier. It consists of an op-amp, a non-binary-weighted capacitor array, and a gain-control block. This non-binary-weighted capacitor array reduces the required number of capacitors and the complexity of the gain-control block. The VGA has been fabricated in a 0.35-mm CMOS process. This work gives the largest gain range of 37 dB per stage, the largest P1 dB of 9.5 dBm at the 3.3-V among the recent VGA circuits available in the literature. The voltage gain is controlled in the range of [-10, 27] dB in a linear-in-dB scale with 16 steps by a 4-bit digital code. The VGA has a bandpass characteristic with a passband of [20 kHz, 8 MHz].

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.13 no.4
• /
• pp.318-330
• /
• 2013

This paper presents a high-linearity low-noise small-size programmable gain amplifier (PGA) based on a new low-noise low-distortion differential amplifier and a proposed reconfiguration technique. The proposed differential amplifier combines an inverter-based differential pair with an adaptive biasing circuit to reduce noise and distortion. The reconfiguration technique saves the chip size by half by utilizing the same differential pair for the input transconductance and load-stage, interchangeably. Fabricated in $0.18-{\mu}m$ CMOS, the proposed PGA shows a dB-linear control range of 21dB in 16 steps from -11 dB to 10 dB with a gain error of less than ${\pm}0.33$ dB, an IIP3 of 7.4~14.5 dBm, a P1dB of -7~1.2 dBm, a noise figure of 13dB, and a 3-dB bandwidth of 270MHz at the maximum gain, respectively. The PGA occupies a chip area of $0.04mm^2$ and consumes only 1.3 mA from the 1.8 V supply.

• ETRI Journal
• /
• v.33 no.6
• /
• pp.897-903
• /
• 2011

A hybrid ${\Delta}{\Sigma}$ modulator for audio applications is presented in this paper. The pulse generator for digital-to-analog converter alleviates the requirement of the external clock jitter and calibrates the coefficient variation due to a process shift and temperature changes. The input resistor network in the first integrator offers a gain control function in a dB-linear fashion. Also, careful chopper stabilization implementation using return-to-zero scheme in the first continuous-time integrator minimizes both the influence of flicker noise and inflow noise due to chopping. The chip is implemented in a 0.13 ${\mu}m$ CMOS technology (I/O devices) and occupies an active area of 0.37 $mm^2$. The ${\Delta}{\Sigma}$ modulator achieves a dynamic range (A-weighted) of 97.8 dB and a peak signal-to-noise-plus-distortion ratio of 90.0 dB over an audio bandwidth of 20 kHz with a 4.4 mW power consumption from 3.3 V. Also, the gain of the modulator is controlled from -9.5 dB to 8.5 dB, and the performance of the modulator is maintained up to 5 nsRMS external clock jitter.

• ETRI Journal
• /
• v.46 no.4
• /
• pp.708-715
• /
• 2024

We propose a 10-GHz 2 × 2 phased-array radio frequency (RF) receiver with an 8-bit linear phase and 15-dB gain control range using 65-nm complementary metal-oxide-semiconductor technology. An 8 × 8 phased-array receiver module is implemented using 16 2 × 2 RF phased-array integrated circuits. The receiver chip has four single-to-differential low-noise amplifier and gain-controlled phase-shifter (GCPS) channels, four channel combiners, and a 50-Ω driver. Using a novel complementary bias technique in a phase-shifting core circuit and an equivalent resistance-controlled resistor-inductor-capacitor load, the GCPS based on vector-sum structure increases the phase resolution with weighting-factor controllability, enabling the vector-sum phase-shifting circuit to require a low current and small area due to its small 1.2-V supply. The 2 × 2 phased-array RF receiver chip has a power gain of 21 dB per channel and a 5.7-dB maximum single-channel noise-figure gain. The chip shows 8-bit phase states with a 2.39° root mean-square (RMS) phase error and a 0.4-dB RMS gain error with a 15-dB gain control range for a 2.5° RMS phase error over the 10 to10.5-GHz band.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.31 no.3A
• /
• pp.356-359
• /
• 2006

A monolithic SiGe HBT variable gain driver amplifier(VGDA) with high dB-linear gain control and high linearity has been developed as a driver amplifier with ground-shielded microstrip lines for 5-GHz transmitters. The VGDA consists of three blocks such as the cascode gain-control stage, fixed-gain output stage, and voltage control block. The circuit elements were optimized by using the Agilent Technologies' ADSs. The VGDA was implemented in STMicroelectronics' 0.35${\mu}m$ Si-BiCMOS process. The VGDA exhibits a dynamic gain control range of 34 dB with the control voltage range from 0 to 2.3 V in 5.15-5.35 GHz band. At 5.15 GHz, maximum gain and attenuation are 10.5 dB and -23.6 dB, respectively. The amplifier also produces a 1-dB gain-compression output power of -3 dBm and output third-order intercept point of 7.5 dBm. Input/output voltage standing wave ratios of the VGDA keep low and constant despite change in the gain-control voltage.

• Proceedings of the IEEK Conference
• /
• 1998.10a
• /
• pp.323-326
• /
• 1998

A LNA(Low Nosise Amplifer) module for the Ka-band satellite transponder has been developed, which is composed of developed two MMIC chips and 50$\Omega$ line. This LNA exhibited noise figure less than 3.12dB, linear gain higher than 32dB from 30.085GHz to 30.885GHz frequency range. Temperature test from $20^{\circ}to$ $60^{\circ}C$ of the LNA Module showed very small noise figure and linear gain variation of 0.2 dB and 0.4dB.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.19 no.9
• /
• pp.1793-1801
• /
• 1994

In this paper, a new method for predicting the 1 dB gain compression point of cascaded N amplifiers is proposed. With the proposed method, the transfer function of each amplifier is derived from scalar data available from the manufacturers data sheet and all transfer functions are producted with scalar in order to also derive the overall transfer function of the subsystem under the assumption that the input and output port of each amplifier are matched. Therefore, the 1 dB gain compression point of the subsystem can be predicted or estimated, reversely, utilizing the overall transfer function obtained with the proposed method. The proposed method can be used irrespective of the number of scalar data but, in this paper, it is analyzed only with two scalar data (linear power gain and 1 dB gain compression point) and three scalar data(linear power gain, 1 dB and 0.5 dB gain compression points). With two sample amplifiers operated in Ku-band, the predicted results by the proposed and previous method, respectively, and the experimental results are together presented in order to confirm its utility.