• Journal of Power Electronics
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• v.13 no.5
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• pp.896-908
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• 2013

Under high grid impedance conditions, it is difficult to guarantee the stability of grid-connected inverters with an LCL filter designed based on ideal grid conditions. In this paper, the theoretical basis for output impedance calculation is introduced. Based on the small-signal model, the d-d channel closed-loop output impedance models adopting the converter-side current control method and the grid-side current control method are derived, respectively. Specifically, this paper shows how to simplify the stability analysis which is usually complemented based on the generalized Nyquist stability criterion (GNC). The stability of each current-controlled grid-connected system is analyzed via the proposed simplified method. Moreover, the influence of the LCL parameters on the stability margin of grid-connected inverter controlled with converter-side current is studied. It is shown that the stability of grid-connected systems is fully determined by the d-d channel output admittance of the grid-connected inverter and the inductive component of the grid impedance. Experimental results validate the proposed theoretical stability analysis.

• Journal of Biomedical Engineering Research
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• v.28 no.1
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• pp.66-74
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• 2007

We have developed a multi-channel, multi-frequency EIT system with operating frequency of 10Hz to 500KHz. The number of digital voltmeters using phase-sensitive demodulation can be varied from 8 to 64 and we found that 16 and 32-channels are most practical. This paper describes the design, implementation, and construction of 16 and 32-channel systems. The performance of the system was thoroughly tested and we found that CMRR of the developed voltmeter is about 85dB with $100{\Omega}$ unbalancing series resistor. The SNR is greater than 99.6dB and the output impedance of the constant current source is $1{\Omega}W$ at least for all frequencies. Imaging experiments using a banana with frequency-dependent conductivity and permittivity show that frequency-difference imaging is possible using the developed system. Future works of animal and human experiments are discussed.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.3
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• pp.312-318
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• 2016

This paper presents a 2-6 GHz GaN HEMT power amplifier monolithic microwave integrated circuit (MMIC) with bridged-T all-pass filters and output-reactance-compensation shorted stubs using the $0.25{\mu}m$ GaN HEMT foundry process that is developed by WIN Semiconductors, Inc. The bridged-T filter is modified to mitigate the bandwidth degradation of impedance matching due to the inherent channel resistance of the transistor, and the shorted stub with a bypass capacitor minimizes the output reactance of the transistor to ease wideband load impedance matching for maximum output power. The fabricated power amplifier MMIC shows a flat linear gain of 20 dB or more, an average output power of 40.1 dBm and a power-added efficiency of 19-26 % in 2 to 6 GHz, which is very useful in applications such as communication jammers and electronic warfare systems.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.9 no.2
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• pp.51-59
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• 2010

In this paper, we propose an inverted type asymmetric Doherty amplifier with optimized efficiency characteristic in wanted output power back-off (OPBO) range according to peak to average power ratio of input signal In order to obtain optimized efficiency of the asymmetric Doherty amplifier in wanted OPBO, peak power ratio between main amplifier and peaking amplifier was determined and then impedance of 90 degrees impedance transformer was obtained by peak power ratio. The offset line length and peak dividing ratio of the asymmetric Doherty amplifier were also calculated. From the measurement results, the proposed amplifier has achieved 40 % drain efficiency and -35 dBc adjacent channel leakage ratio at the average output power of 48.7 dBm for CDMA 2000 1x 3-FA test signal.

• ETRI Journal
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• v.32 no.1
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• pp.151-153
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• 2010

A highly efficient linear and compactly integrated series-type Doherty power amplifier (PA) has been developed for wideband code-division multiple access handset applications. To overcome the size limit of a typical Doherty amplifier, all circuit elements, such as matching circuits and impedance transformers, are fully integrated into a single monolithic microwave integrated circuit (MMIC). The implemented PA shows a very low idle current of 25 mA and an excellent power-added efficiency of 25.1% at an output power of 19 dBm by using an extended Doherty concept. Accordingly, its average current consumption was reduced by 51% and 41% in urban and suburban environments, respectively, when compared with a class-AB PA. By adding a simple predistorter to the PA, the PA showed an adjacent channel leakage ratio better than -42 dBc over the whole output power range.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.10 no.5
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• pp.99-104
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• 2011

This paper presents a high power and high efficiency unbalanced Doherty power amplifier used to extend the output power back-off (OPBO). The proposed unbalanced amplifier uses the same type of transistors in both the main amplifier and the peaking amplifier, similar to a conventional symmetric Doherty amplifier. The unbalanced amplifier can have the impedance of a ${\lambda}/4$ transformer located at the output of the main amplifier modified. This enables the OPBO to exceed 6 dB, the maximum OPBO for a conventional symmetric Doherty amplifier. The efficiency and linearity performance of the unbalanced Doherty amplifier are almost same as those found for the asymmetric Doherty amplifier, even though the unbalanced Doherty amplifier structure is simpler than the asymmetric Doherty structure. In order to verify the proposed amplifier performance, a 46 W Doherty amplifier has been both simulated and measured using a CDMA2000 1FA signal. From the measured results, the proposed unbalanced Doherty amplifier achieved an added power efficiency of 38 % and an adjacent channel power ratio of -34 dBc at a 885 kHz offset frequency and -35.6 dBc at a 1.98 MHz offset frequency.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.7
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• pp.620-626
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• 2015

In this paper, a 2~6 GHz wideband GaN power amplifier MMIC is designed and fabricated using a second-order all-pass filter for input impedance matching and an LC parallel resonant circuit for minimizing an output reactance component of the transistor. The second-order all-pass filter used for wideband lossy matching is modified in an asymmetric configuration to compensate the effect of channel resistance of the GaN transistor. The power amplifier MMIC chip that is fabricated using a $0.25{\mu}m$ GaN HEMT foundry process of Win Semiconductors, Corp. is $2.6mm{\times}1.3mm$ and shows a flat linear gain of about 13 dB and input return loss of larger than 10 dB. Under a saturated power mode, it also shows output power of 38.6~39.8 dBm and a power-added efficiency of 31.3~43.4 % in 2 to 6 GHz.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.1312-1315
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• 2002

This research describes the design of a fully integrated fractional-N frequency synthesizer intended for the local oscillator in IMT-2000 system using 0.18-$\mu\textrm{m}$ CMOS technology and 1.8-V single power supply. The designed fractional-N synthesizer contains following components. Modified charge pump uses active cascode transistors to achieve the high output impedance. A multi-modulus prescaler has modified ECL-like D flip-flop with additional diode-connected transistors for short transient time and high frequency operation. And phase-frequency detector, integrated passive loop filter, LC-tuned VCO having a tuning range from 1.584 to 2.4 ㎓ at 1.8-V power supply, and higher-order sigma-delta modulator are contained. Finally, designed frequency synthesizer provides 5 ㎒ channel spacing with -122.6 dBc/Hz at 1 ㎒ in the WCDMA band and total output power is 28 mW.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.30 no.2
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• pp.104-110
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• 2019

In this paper, a complementary metal oxide semiconductor(CMOS) power amplifier(PA) integrated circuit operating in the 900 MHz band for long-term evolution(LTE) communication systems is presented. The output matching network based on a transformer was implemented on a printed circuit board for low loss. Simultaneously, to achieve high efficiency of the PA, the second harmonic impedances are controlled. The CMOS PA was fabricated using a $0.18{\mu}m$ CMOS process and measured using an LTE uplink signal with a bandwidth of 10 MHz and peak to average power ratio of 7.2 dB for verification. The implemented CMOS PA module exhibits a power gain of 24.4 dB, power-added efficiency of 34.2%, and an adjacent channel leakage ratio of -30.1 dBc at an average output power level of 24.3 dBm.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.7 s.361
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• pp.54-61
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• 2007

A variable gain low noise amplifier (VG-LNA) implemented in TSMC 0.18 um process is presented. This VG-LNA is designed of two stage amplifier, and its gain is controlled by the shunt feedback loop composed of a gain control transistor (GCT) and a coupling capacitor in second stage. The channel resistance of GCT in the shunt feedback loop influences the input and output stages of a second stage by the Miller effect. Total gain of the proposed VG-LNA is changed by two factors, the load impedance reduction and the interstage mismatch by controlling the channel resistance of the GCT. Consequently, by adding a shunt feedback with a gain control transistor, this proposed VG-LNA achieves both wide gain tuning range of 37 dB and continuous gain control simultaneously.