• 전자공학회논문지A
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• 제32A권12호
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• pp.159-165
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• 1995

A gate-recessed structure is introduced to SOI MOSFET's in order to increase the source-to-drain breakdown voltage. A significant increase in the breakdown voltage is observed compared with that of a planar single source/drain SOI MOSFET without inducing the appreciable reduction of the current drivability. We have analyzed the origin of the breakdown voltage improvement by the substrate current measurements and 2-D device simulations, and shown that the breakdown voltage improvement is caused by the reductions in the impact ionization rate and the parasitic bipolar current gain.

• 대한전기학회논문지:전력기술부문A
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• 제52권8호
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• pp.481-485
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• 2003

In electric railway system, potential of rail has been risen, for return-current flows through rail. The magnitude of rising voltage is different to railway feed system, ground admittance of rail and the load current. If rising voltage of rail is large, electric shock can be occurred to passengers and maintenance- worker, In this paper, we estimate the rising voltage of rail in high speed railway system and check the safety to human beings.

• 조명전기설비학회논문지
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• 제14권4호
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• pp.39-47
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• 2000

본 논문에서는 입력전류 추정에 의한 전밥형 PWM 컨버터의 정상상태 및 과도상태 특성을 개선하기 위하여 정현추종제어기를 제안한다. 그리고, 입력전류의 추정방법과 제어기의 구성에 대해서 논의된다. DC 출력전압은 PI제어기로 제어되며, AC 입력전류를 직접추총 제어하는 정현추종 전류제어기가 입력전류 제어기로 사용된다. 정현추종 전류제아기는 좌표변환 알고리즘 없이 사용가능 하므로 제어계를 간소화 할 수 있다. 입력전류 제어계의 전달함수로부터 입력전류의 정상상태오차가 0이 되고, 입력전압의 동에 대해서도 제안한 제어계는 영향을 받지 않는다는 것을 알 수 있다. 아울러 제안한 방법에 대한 타당성이 시뮬레이션 및 부하, 입력 전압 변동에 대한 실험결과로부터 확인할 수 있다.

• 대한전자공학회논문지SD
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• 제45권3호
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• pp.54-59
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• 2008

본 논문에서는 광범위 출력전압을 위한 고정밀 BiCMOS cascode 전류미러를 제안하였다. 제안한 전류미러는 베이스 전류에러를 보상하는 BJT 전류미러를 기본으로 하고 있다. NMOS-NMOS cascode 구조 대신에 npn-NMOS cascode 구조를 사용하여, 출력저항과 출력전압 범위를 증가시켰다. npn 전류 복사 트랜지스터는 입력전류를 출력전류로 복사하고, NMOS 트랜지스터는 출력저항을 증가시켜 정밀한 전류 복사를 가능케 한다. 제안한 전류미러는 광범위 출력전압에서 정밀하게 전류를 복사한다. 5V/16V 0.5um BCD 공정을 이용하여 제작한 칩을 측정하여 검증하였고, $0.3V{\sim}16V$의 출력전압 범위에서 전류 에러는 $-2.5%{\sim}1.0%$이다.

• 전력전자학회논문지
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• 제24권3호
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• pp.153-160
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• 2019

This study proposes a current source-type pulse generator to improve output voltage and current waveforms under a capacitively coupled plasma (CCP) system. The proposed circuit comprises two parallel-connected current source-type converters. These converters can satisfy the required output waveforms of plasma processing. The parallel-connected converters operate without reverse current fault by applying a time-delay control technique. Conventional voltage source converters based on pulse power supply exhibit drawbacks in short-circuit current, and problems occur when they are applied to a CCP system. The proposed pulse power supply based on a current source converter fundamentally solves the short-circuit current problem. Therefore, this topology can improve the voltage and current accuracy of a CCP system.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년도 제37회 하계학술대회 논문집 A
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• pp.208-209
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• 2006

Voltage Transformer is used to transform high voltage into low voltage to input signal of protection relay. Most of the Voltage Transformers use the iron core which maximizes the flux linkage. The ratio of the Voltage Transformer depends on the transformer turns ratio. The current which flows in the Voltage Transformer has non-linear characteristic caused by hysteresis of the iron core, it causes a voltage loss in the winding impedances which makes measurement errors. This paper describes an error compensation method considering hysteresis characteristic. The proposed compensation method improves error by calculating the primary current from the exciting current of the hysteresis loop in the Voltage Transformer, compensating the voltage loss.

• 전기학회논문지P
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• 제59권3호
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• pp.325-329
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• 2010

Capacitor has been used principally for the power factor compensation long ago. However now it does as passive filter to reduce harmonics of nonlinear load with reactor. Most of the customer's low-voltage feeder has been designed with approximately balanced and connected at the 3 phase four wire system. But voltage and current unbalance is appeared by the mixing operation of single or three phase load etc. The addition of reactor at the condenser may rise its terminal voltage. Voltage and current values above rating can act on electrical stress on the condenser. In this paper, we calculated and measured that voltage, current and capacity of condenser are changed under the voltage balance. We conclude that magnitude and deviation of phase voltage act on major point of electrical stress.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1992년도 하계학술대회 논문집 B
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• pp.794-798
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• 1992

We present an optical Voltage and current sensor using $BSO(Bi_{12}SiO_{20})$ monocrystal. The voltage and current sensor consist of PBS(Polarizing Beam Splitter), 1/4 wavelength plate, ZnSe, Selfoc lens, LED, and PIN-PD etc. Magnetic core was made using permalloy for applying magnetic field to current sensor effectively. Current was measured from 100 to 1,600 ampere and accuracy was about ${\pm}$5%. The accuracy could be improved to ${\pm}$l% after reducing the nonlinear property of BSO crystal using our own program in PC (IBM286). We noticed that these data were not influenced by 154,000 voltage at all. Applied voltage was reduced to 1/20 using capacitors. And experiment was carried out up to 450V of the reduced voltage. The data fran optical voltage sensor was similar to that from conventional voltage sensor. The accuracy of the data was within about ${\pm}$1%.

• JSTS:Journal of Semiconductor Technology and Science
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• 제12권1호
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• pp.99-106
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• 2012

For CMOS technology of 65 nm and beyond, the gate leakage current can not be negligible anymore. In this paper, the impact of the gate leakage current in ring voltage-controlled oscillator (VCO) on phase-locked loop (PLL) is analyzed and modeled. A voltage -to-voltage (V-to-V) circuit is proposed to reduce the voltage ripple on $V_{ctrl}$ induced by the gate leakage current. The side effects induced by the V-to-V circuit are described and optimized either. The PLL design is based on a standard 65 nm CMOS technology with a 1.8 V power supply. Simulation results show that 97 % ripple voltage is smoothed at 216 MHz output frequency. The RMS and peak-to-peak jitter are 3 ps and 14.8 ps, respectively.

• Journal of Power Electronics
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• 제13권5호
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• pp.829-840
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• 2013

The modified sinusoidal pulse-width modulation (SPWM) is one of the PWM techniques used in three-phase AC-DC buck converters. The modified SPWM works without the current sensor (the converter is current sensorless), improves production of sinusoidal AC current, enables obtainment of near-unity power factor, and controls output voltage through modulation gain (ranging from 0 to 1). The main problem of the modified SPWM is the huge starting current and voltage (during transient) that results from a large step change from the reference voltage. When the load changes, the output voltage significantly drops (through switching losses and non-ideal converter elements). The single-input single-output (SISO) approach with minor-loop voltage feedback controller presented here overcomes this problem. This approach is created on a theoretical linear model and verified by discrete-model simulation on MATLAB/Simulink. The capability and effectiveness of the SISO approach in compensating start-up current/voltage and in achieving zero steady-state error were tested for transient cases with step-changed load and step-changed reference voltage for linear and non-linear loads. Tests were done to analyze the transient performance against various controller gains. An experiment prototype was also developed for verification.