• 전기학회논문지
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• 제58권3호
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• pp.627-631
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• 2009

This paper presents a novel current steering cell matrix DAC(digital-to-analog converter) architecture to reduce decoder area. The current cell matrix of a existing architecture is selected by columns and lows thermometer code decoder of input bits. But The current cell matrix of a proposal architecture is divided 2n by the thermometer code decoder of upper input bits and are selected by the thermometer code decoder of middle and lower input bits. Because of this configuration, decoder numbers have increased. But the gate number that composed of decoder has decreased. In case of the designed 8 bit current steering cell matrix DAC, the gate number of decoder has decreased by about 55% in comparison with a existing architecture.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1998년도 춘계학술대회 논문집
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• pp.243-246
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• 1998

This paper presents a 6-bit self-calibrated D/A converter designed with current cell matrix structure. This structure is based on the current-cell matrix configuration using a regulated gate cascode current cell with 3-way switch. using from CMOS process and 5V power supply, the simulated conversion rate is 45.78MHz and the average mismatching properties among current sources are reduced to 0.02% and 0.005%, respectively when 1% and 0.5% errors of current sources are considered.

• 한국세라믹학회지
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• 제32권2호
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• pp.189-196
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• 1995

Materials retaining electrolyte of a phosphoric acid fuel cell (PAFC) have been prepared with SiC powder to SiC whisker mixing ratios of 1:1, 1:2, 1:3, 1:4, 0:1 by a tape casting method. When 3wt% dispersant (sorbitan monooleate) is added to a matrix, the porosity of the matrix decreases a little while the bubble pressure and area of the matrix increase remarkably in comparison with no dispersant content. Effect of the electrolyte resistance and the polarization resistance on perfomance of a PAFC has been investigated using A.C. impedance spectroscopy. With the increase of whisker content, the electrolyte resistance decreases due to the increase of porosity and acid absorbancy, and the polarization resistance increases due to the increase of surface roughness. The polarization resistance affects current density predominantly at the higher potential than 0.7V becuase the polarization resistance is considrably larger than the electrolyte resistance. Both the electrolyte resistance and the polarization resistance affect current density near 0.7V of the fuel cell operating potential because they have similar values. The electrolyte resistance affects current density predominantly at the lower potential than the fuel cell operating potential because the electrolyte resistance is larger than the polarization resistance.

• 한국세라믹학회지
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• 제29권8호
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• pp.587-592
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• 1992

Sheets of SiC-SiC whisker maxed matrix were prepared from the mixed slurry of SiC whisker and SiC matrix by the rolling method. With the increase of SiC whisker, the pore size, the porosity and the phosphoric acid absorbency of the matrix were increased, while the bubble pressure was decreased. The activation energy for the transfer of H+ ion was decreased with the increase of mixing ratio of SiC whisker to the SiC matrix from the measurement of hydrogen ion conductivity. The activation energy was evaluated as 0.25 eV when the mixing ratio of SiC whisker to the SiC matrix was 1 : 2 and the activation energy was 0.16 eV for the 2 : 1 matrix. It means that SiC whisker matrix contributes to attain a better microstructure for the diffusion of hydrogen ion. From the measurement of single cell performance of matrix with various mixing ratio, it is concluded that if SiC-SiC whisker maxed matrix has a sufficient bubble pressure to prevent the crossover of H2 gas, the current density of a fuel cell is increased with the increase of acid absorbency of the matrix. Current density was improved from 140 mA/$\textrm{cm}^2$ for 0.25 mm thickness of matrix to 170 mA/$\textrm{cm}^2$ for the 0.20 mm one at 700 mV.

• Transactions on Electrical and Electronic Materials
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• 제10권2호
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• pp.44-48
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• 2009

A simulation study of a 10-bit two-stage DAC was done by using a conventional current switch cell. The DAC adopts the segmented architecture in order to reduce the circuit complexity and the die area. The 10-bit CMOS DAC was designed in 2 blocks, a unary cell matrix for 6 MSBs and a binary weighted array for 4 LSBs, for fabrication in a 0.35-${\mu}m$ CMOS process. To cancel the accumulation of errors in each current cell, a symmetrical switching sequence is applied in the unary cell matrix for 6 MSBs. To ensure high-speed operation, a decoding circuit with one stage latch and a cascode current source were developed. Simulations show that the maximum power consumption of the 10-bit DAC is 74 mW with a sampling frequency of 100 MHz.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2009년도 제38회 동계학술대회 초록집
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• pp.433-433
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• 2010

A microplasma current switch (MPCS) for a device operated in a current mode like organic light-emitting diodes (OLEDs), which features matrix addressability and current switching, is presented as well as its architecture and operational principle. The MPCS utilizes the intrinsic memory and conductivity of plasmas to achieve matrix addressability and current switching. We have fabricated a $100\;mm\;{\times}\;100\;mm$ MPCS panel in which its cell pitch is $1080\;{\mu}m\;{\times}\;1080\;{\mu}m$. The matrix addressability and current switching were verified. In addition, the current-voltage (I-V) characteristic of the unit cell was measured when plasmas were ignited. In principle, the scheme of the MPCS is equivalent to that of a double Langmuir probe diagnosing plasma parameters except for their relative dimensions to a plasma volume. Accordingly, the I-V characteristic was analyzed by a double Langmuir probe theory, and the plasma density and electron temperature were estimated from the I-V curve using a collisional double Langmuir probe theory.

• 대한전자공학회논문지SD
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• 제40권9호
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• pp.685-691
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• 2003

본 논문에서는 고속 통신 시스템 응용을 위한 12b 100 MS/s CMOS D/A 변환기(DAC) 회로를 제안한다. 제안하는 DAC는 전력소모, 면적, 선형성 및 글리치 에너지 등을 고려하여, 상위 8b는 단위 전류셀 매트릭스 (unit current-cell matrix)로 나머지 하위 4b는 이진 전류열 (binary-weighted array)로 구성하였다. 제안하는 DAC는 동적 성능을 향상시키기 위해 새로운 구조의 스위치 구동 회로를 사용하였다. 시제품 DAC회로 레이아웃을 위해서는 캐스코드 전류원을 단위 전류셀 스위치 매트릭스와 분리하였으며, 제안하는 칩은 0.35 um single-poly quad-metal CMOS 공정을 사용하여 제작되었다. 측정된 시제품의 DNL 및 INL은 12b 해상도에서 각각 ±0.75 LSB와 ±1.73 LSB이내의 수준이며, 100 MS/s 동작 주파수와 10 MHz 입력 주파수에서 64 dB의 SFDR을 보여준다. 전력 소모는 3 V의 전원 전압에서 91 mW이며, 칩 전체 크기는 2.2 mm × 2.0 mm 이다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제3권4호
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• pp.211-216
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• 2003

This work describes a 3 V 12b 100 MS/s CMOS digital-to-analog converter (DAC) for high-speed communication system applications. The proposed DAC is composed of a unit current-cell matrix for 8 MSBs and a binary-weighted array for 4 LSBs, trading-off linearity, power consumption, chip area, and glitch energy with this process. The low-glitch switch driving circuits are employed to improve linearity and dynamic performance. Current sources of the DAC are laid out separately from the current-cell switch matrix core block to reduce transient noise coupling. The prototype DAC is implemented in a 0.35 um n-well single-poly quad-metal CMOS technology and the measured DNL and INL are within ${\pm}0.75$ LSB and ${\pm}1.73$ LSB at 12b, respectively. The spurious-free dynamic range (SFDR) is 64 dB at 100 MS/s with a 10 MHz input sinewave. The DAC dissipates 91 mW at 3 V and occupies the active die area of $2.2{\;}mm{\;}{\times}{\;}2.0{\;}mm$

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2009년도 9th International Meeting on Information Display
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• pp.854-857
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• 2009

The concept of a microplasma current switch for a device operated in a current mode like organic light-emitting diodes, which features matrix addressability and current switching, is presented as well as its architecture and operational principle. To verify the concept, we have fabricated a 100 mm ${\times}$ 100 mm microplasma current switch panel with a cell pitch of $1080{\mu}m{\times}1080{\mu}m$. Moreover, the current-voltage measurements of the unit cell are performed for three different driving voltage amplitudes. They show the characteristic of an asymmetric floating double probe diagnosing plasmas.

• 전자공학회논문지C
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• 제35C권4호
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• pp.50-59
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• 1998

This paper describes a 3.3V 8bit CMOS digital to analog converter (DAC) with two state current cell metrix architecture which consists of a 4 MSB and a 4 LSB current matrix stage. The symmetric two stage current cell matrix architecture allow the designed DAC to reduce hot only a complexity of decoding logics, but also a number of wider swing cascode curent mirros. The designed DAC with an active chip area of 0.8 mm$_{2}$ is fabricated by a 0.8 .mu.m CMOS n-well standard digital process. The experimental data shows that the rise/fall time, the settling time, and INL/DNL are6ns, 15ns, and a less than .+-.0.8/.+-.0.75 LB, respectively. The designed DAC is fully operational for the power supply down to 2.0V, such that the DAC is suitable for a low voltage and a low power system application. The power dissipation of the DAC with a single power supply of 3.3V is measured to be 34.5mW.