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A 3 V 12b 100 MS/s CMOS DAC for High-Speed Communication System Applications  

배현희 (서강대학교 전자공학과)
이명진 (서강대학교 전자공학과)
신은석 (서강대학교 전자공학과)
이승훈 (서강대학교 전자공학과)
김영록 (서강대학교 전자공학과)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.40, no.9, 2003 , pp. 685-691 More about this Journal
Abstract
This work describes a 3 V 12b 100 MS/s CMOS digital-to-analog converter (DAC) for high-speed communication system applications. The proposed DAC is composed of a unit current-cell matrix for 8 MSBs and a binary-weighted array for 4 LSBs, considering linearity, power consumption, chip area, and glitch energy. The low-glitch switch driving circuit is employed to improve the linearity and the dynamic performance. Current sources of the DAC are laid out separately from the current-cell switch matrix core. The prototype DAC is implemented in a 0.35 urn n-well single-poly quad-metal CMOS technology. The measured DNL and INL of the prototype DAC are within $\pm$0.75 LSB and $\pm$1.73 LSB, respectively, and the spurious-free dynamic range (SFDR) is 64 dB at 100 MS/s with a 10 MHz input sinewave. The DAC dissipates 91 mW at 3 V and occupies the active die area of 2.2 mm ${\times}$ 2.0 mm.
Keywords
digital-to-analog converter; current-steering; CMOS; current-cell matrix; binary-weighted array;
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1 K. Lakshmikumar, R. Hadaway, and M.Copeland, 'Characterization and modeling of mismatch in MOS transistors for precision analog design,' IEEE J. Solid-State Circuits, vol. SC-21, pp. 1057-1066, Dec. 1986
2 A. Bosch, M. Borremans, J. Vandenbussche, G. Plas, A. Marques, J. Bastos, M. Steyaert, G. Gielen, and W. Sansen, 'A 12b 200 MHz low glitch CMOS DAC,' in Proc. IEEE Custom Integrated Circuits Conf., May 1998, pp. 11.7.1-11.7.4
3 C. Lin and K. Bult, 'A 10b 500 MSample/s CMOS DAC in 0.6mm2,' IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 1948-1958, Dec. 1998   DOI   ScienceOn
4 S. H. Lee and Y. Jee, 'A temperature and supply-voltage insensitive CMOS current reference,' IEICE Trans on Electronics, vol. E82-C, no. 8, pp. 1562-1566, Aug. 1999
5 A.Van den Bosch, et al., 'A 10b 1 GSample/s nyquist current-steering CMOS DAC,' IEEE J. Solid-State Circuits, vol. 36, no. 3, pp. 315-324, Mar. 2001   DOI   ScienceOn
6 A. Van den Bosch, et al., 'A 12b 500 MSample/s Current-Steering CMOS DAC,' in ISSCC Dig. Tech. Papers, Feb. 2001, pp. 366-367   DOI
7 P. Hendriks, 'Specifying communication DACs,' IEEE Spectrum, pp. 58-69, July 1997   DOI   ScienceOn
8 Jussi Pirkkalaniemi, et al., 'A 14b 40 MS/s DAC with current mode deglitcher,' Proc IEEE ISCAS 2002, vol. 1, 2002, pp. 121-124
9 Crippa, P. Conti, M. Turchetti, C., 'A statistical methodology for the design of high-performance current steering DAC's,' Proc. IEEE ISCAS 2001, vol. 5, 2001, pp. 311-314
10 Geert A.M. Van der Plas, et al., 'A 14b intrinsic accuracy Q2 random walk CMOS DAC,' IEEE J. Solid-State Cirucuits, vol. 34, no. 12, pp. 1708-1718, Dec. 1999   DOI   ScienceOn
11 J. Bastos, A. Marques, M. Steyaert, and W. Sansen, 'A 12-bit intrinsic accuracy high-speed CMOS DAC,' IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 1959-1969, Dec, 1998   DOI   ScienceOn
12 H. Kohno, Y. Nakamura, A. Kondo, H. Amishiro, T. Miki, K. Okada, 'A 350-MS/s 3.3-V 8-bit CMOS DAC using a delayed driving scheme,' in Proc. IEEE Custom Integrated Circuits Conf., May 1995, pp. 10.5.1-10.5.4
13 J. Park, S. C. Lee, J. S. Yoon, and S. H. Lee, 'A 3V 10b 100 MS/s digital-to-analog converter for cable modem applications,' IEEE Trans. on Consumer Electronics, vol. 46, no. 4, pp. 1043-1047, Nov. 2000   DOI   ScienceOn
14 J. Vandenbussche, G. Plas, A. Bosch, W. Daems, G. Gielen, M.Seyaert, and W. Sansen, 'A 14b 150 MSample/s update rate Q2 ranodm walk CMOS DAC,' ISSCC Dig. Tech. Papers, Feb. 1999, pp. 146-147
15 A. R. Bugeja, B. S. Song, P. L. Rakers, and S. F. Gillig, 'A 14b 100 MSample/s CMOS DAC designed for spectral performance,' ISSCC Dig. Tech. Papers, Feb. 1999, pp. 148-149   DOI
16 B. Razavi, Principles of Data Conversion System Design, New York : IEEE Press, 1995