• JSTS:Journal of Semiconductor Technology and Science
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• 제10권2호
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• pp.130-133
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• 2010

This paper presents a study of the influence of variation of counter doping thickness on short channel effect in symmetric double-gate (DG) nano MOSFETs. Short channel effects are estimated from the computed values of current-voltage (I-V) characteristics. Two dimensional Quantum transport equations and Poisson equations are used to compute DG MOSFET characteristics. We found that the transconductance ($g_m$) and the drain conductance ($g_d$) increase with an increase in p-type counter-doping thickness ($T_c$). Very high value of transconductance ($g_m=38\;mS/{\mu}m$) is observed at 2.2 nm channel thickness. We have established that the threshold voltage of DG MOSFETs can be tuned by selecting the thickness of counter-doping in such device.

• JSTS:Journal of Semiconductor Technology and Science
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• 제8권1호
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• pp.11-20
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• 2008

The structure of 2-bit/cell flash memory device was characterized for sub-50 nm non-volatile memory (NVM) technology. The memory cell has spacer-type storage nodes on both sidewalls in a recessed channel region, and is erased (or programmed) by using band-to-band tunneling hot-hole injection (or channel hot-electron injection). It was shown that counter channel doping near the bottom of the recessed channel is very important and can improve the $V_{th}$ margin for 2-bit/cell operation by ${\sim}2.5$ times. By controlling doping profiles of the channel doping and the counter channel doping in the recessed channel region, we could obtain the $V_{th}$ margin more than ${\sim}1.5V$. For a bit-programmed cell, reasonable bit-erasing characteristics were shown with the bias and stress pulse time condition for 2-bit/cell operation. The length effect of the spacer-type storage node is also characterized. Device which has the charge storage length of 40 nm shown better ${\Delta}V_{th}$ and $V_{th}$ margin for 2-bit/cell than those of the device with the length of 84 nm at a fixed recess depth of 100 nm. It was shown that peak of trapped charge density was observed near ${\sim}10nm$ below the source/drain junction.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1994년도 추계학술대회 논문집
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• pp.210-215
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• 1994

In the CMOS device, Counter doping is needed to adjust threshold voltage because of the difference between n-MOSFET and p-MOSFET well doping concentration when n+ polysilicon gate is used. Therefore buried channel is formed in the p-channel MOSFET degrading properties. So well doping concentration and doping condition should be considered in fabrication process and device design. Here we are to extract the initial process condition using simulation and fabricate p-MOSFET device and then compare the subthreshold characteristics of simulated and fabricated device.

• JSTS:Journal of Semiconductor Technology and Science
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• 제10권3호
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• pp.240-250
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• 2010

Double Gate MOSFETs (DG MOSFETs) with doping in one or two thin layers of an otherwise intrinsic channel are simulated to obtain the transport characteristics, threshold voltage and leakage current. Two different device structures- one with doping on two layers near the top and bottom oxide layers and another with doping on a single layer at the centre- are simulated and the variation of device parameters with a change in doping concentration and doping layer thickness is studied. It is observed that an n-doped layer in the channel reduces the threshold voltage and increases the drive current, when compared with a device of undoped channel. The reduction in the threshold voltage and increase in the drain current are found to increase with the thickness and the level of doping of the layer. The leakage current is larger than that of an undoped channel, but less than that of a uniformly doped channel. For a channel with p-doped layer, the threshold voltage increases with the level of doping and the thickness of the layer, accompanied with a reduction in drain current. The devices with doped middle layers and doped gate layers show almost identical behavior, apart from the slight difference in the drive current. The doping level and the thickness of the layers can be used as a tool to adjust the threshold voltage of the device indicating the possibility of easy fabrication of ICs having FETs of different threshold voltages, and the rest of the channel, being intrinsic having high mobility, serves to maintain high drive current in comparison with a fully doped channel.

• 전자공학회논문지D
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• 제35D권12호
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• pp.53-58
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• 1998

다결정 실리콘 박막 트랜지스터를 이용한 회로의 성능 향상을 위하여 새로운 구조의 4-terminal buried channel poly-Si TFT(BCTFT)를 설계하고 제작하였다. BCTFT는 moderate 도핑이 된 buried channel을 이용하므로 기존의 다결정 실리콘 TFT보다 ON-전류와 전계 효과 이동도가 n-형과 p-형 소자 각각 5배와 10배 향상되었다. BCTFT는 moderate 도핑된 buried 채널과 counter 도핑된 body 사이의 junction 공핍에 의하여 캐리어의 이동이 억제 되므로 OFF-전류가 증가하지 않았다.

• Bulletin of the Korean Chemical Society
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• 제32권5호
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• pp.1635-1639
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• 2011

An efficient and novel positive charge-doping on the sidewalls of multi-walled carbon nanotubes has been achieved in the presence of tetrahydrofuran as a dopant and Lewis acidic ionic liquids, [bmim]$Sb_nF_{5n+1}$ (n ${\geq}$ 2; bmim = 1-butyl-3-methylimidazolium), as an activator, leaving air-stable derivatives having positively charged sidewalls and the counter anions, [MWCNT$^{y+}$][SbF$_6^-$]$_y$ (MWCNT = multi-walled carbon nanotube). The derivatization took place very fast in one-pot and under mild reaction conditions. The ionic structure enabled a tunable dissolution of the derivatives in various solvents through anion exchange.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 하계학술대회 논문집 Vol.8
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• pp.111-111
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• 2007

Further scaling the semiconductor devices down to low dozens of nanometer needs the extremely shallow depth in junction and the intentional counter-doping in the silicon gate. Conventional ion beam ion implantation has some disadvantages and limitations for the future applications. In order to solve them, therefore, plasma source ion implantation technique has been considered as a promising new method for the high throughputs at low energy and the fabrication of the ultra-shallow junctions. In this paper, we study about the effects of DC bias and base pressure as a process parameter. The diluted mixture gas (5% $PH_3/H_2$) was used as a precursor source and chamber is used for vacuum pressure conditions. After ion doping into the Si wafer(100), the samples were annealed via rapid thermal annealing, of which annealed temperature ranges above the $950^{\circ}C$. The junction depth, calculated at dose level of $1{\times}10^{18}/cm^3$, was measured by secondary ion mass spectroscopy(SIMS) and sheet resistance by contact and non-contact mode. Surface morphology of samples was analyzed by scanning electron microscopy. As a result, we could accomplish the process conditions better than in advance.

• 한국결정성장학회지
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• 제9권6호
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• pp.574-579
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• 1999

암모니아가스를 역류시키는 수평식 유기금속 화학기상증착장치를 제작하였으며, 유체흐름에 관한 레이놀즈 수 및 열대류에 관한 레일리 수가 각각 4.5와 215.8이 되도록 하여 GaN 박막을 성장하였다. 이러한 특성변수에서 박막을 성장할 경우 비교적 양호한 박막의 결정특성, 전기적 특성 및 광학적 특성을 갖게 함을 확인하였다. 결정 내의 전위밀도는 $2.6{\times}10^8/\textrm {cm}^2$ 정도이었고, Si으로 도핑된 n-GaN 박막의 전자에 의한 운반자 농도와 이동도는 각각 $10^{17}$~$10^{18}/{\textrm}{cm}^3$ 과 200~400$\textrm{cm}^2$/V.sec의 범위를 갖으며 Mg을 도핑하여 후속열처리로 활성화시킨 p-GaN 박막은 정공에 의한 운반자 농도가 $8\times 10^{17}/{\textrm}{cm}^3$ 정도임을 확인하였다.

• 전기화학회지
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• 제13권3호
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• pp.211-216
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• 2010

전해액 상용성의 boron trifluoride lithium methacrylate ($BF_3$LiMA)를 기본으로 하는 겔 고분자 전해질 (gel polymer electrolytes, GPE)에서 $BF_3$LiMA의 농도가 이온전도도, 전기화학적 안정성에 미치는 영향을 AC impedance 측정법과 linear sweep voltammetry (LSV)를 통하여 평가하였다. 그 결과 $BF_3$LiMA가 4wt% (고분자함량 21 wt%)일 때, 상온 이온전도도가 $5.3{\times}10^{-4}Scm^{-1}$로서 가장 높게 관찰되었으며 4 wt% 전후로 다시 감소하였다. $BF_3$LiMA 기반의 GPE는 음이온이 고정되어 있는 자기-도핑형 계열로서 우수한 전기화학적 안정성을 확인하였다. 한편 $BF_3$LiMA 기반 GPE는 리튬금속과 비교적 불안정한 계면반응성을 보여주었지만 흑연/GPE/흑연, LCO/GPE/LCO에서는 높은 계면안정성을 형성하였다. 따라서 $BF_3$LiMA 기반의 GPE를 통하여 높은 상온 이온전도도와 전기화학적 안정성 및 흑연과 LCO 양극산화물에 대한 우수한 계면특성을 확보할 수 있었다.

• 전기화학회지
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• 제14권4호
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• pp.208-213
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• 2011

합성된 $BF_3LiMA$ 리튬염을 단량체로 사용하는 고체 고분자전해질을 제조하고 $BF_3LiMA$의 농도가 이온전도도에 미치는 영향 및 전기화학적 안정성을 교류임피던스 측정법과 선형전위주사법을 통하여 평가하였다. 그 결과 $BF_3LiMA$가 12.9 wt%인 고체 고분자전해질에서 $7.71{\times}10^{-6}S\;cm^{-1}$의 가장 높은 $25^{\circ}C$ 이온전도도가 관찰되었으며 이 값을 전후로 이온전도도는 다소 감소하는 경향이 나타났다. 이러한 결과는 저농도의 $BF_3LiMA$에서 발생할 수 있는 리튬염의 부족과 고농도의 $BF_3LiMA$에서는 발생할 수 있는 고분자기질의 유동성 감소가 원인으로 해석된다. 또한 $BF_3LiMA$ 기반의 고체 고분자전해질은 음이온이 고정되어 있는 자기-도핑형 계열로서 $60^{\circ}C$에서 6.0 V까지 우수한 전기화학적 안정성을 보여주었다.