• JSTS:Journal of Semiconductor Technology and Science
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• 제13권5호
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• pp.473-481
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• 2013

A fractional folding analog-to-digital converter (ADC) with a novel arithmetic digital encoding technique is discussed. In order to reduce the asymmetry errors of the boundary conditions for the conventional folding ADC, a structure using an odd number of folding blocks and fractional folding rate is proposed. To implement the fractional technique, a new arithmetic digital encoding technique composed of a memory and an adder is described. Further, the coding errors generated by device mismatching and other external factors are minimized, since an iterating offset self-calibration technique is adopted with a digital error correction logic. A prototype 8-bit 1GS/s ADC has been fabricated using an 1.2V 0.13 um 1-poly 6-metal CMOS process. The effective chip area is $2.1mm^2$(ADC core : $1.4mm^2$, calibration engine : $0.7mm^2$), and the power consumption is 88 mW. The measured SNDR is 46.22 dB at the conversion rate of 1 GS/s. Both values of INL and DNL are within 1 LSB.

• Journal of Power Electronics
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• 제16권2호
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• pp.654-665
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• 2016

The pumping of electric power from photovoltaic (PV) farms is normally carried out using transformers, which require heavy mounting structures and are thus costly, less efficient, and bulky. Therefore, transformerless schemes are developed for the injection of power into the grid. Compared with the H4 inverter topology, the H6 topology is a better choice for pumping PV power into the grid because of the reduced common mode current. This paper presents how the perturb and observe (P&O) algorithm for maximum power point tracking (MPPT) can be implemented in the H6 inverter topology along with the improved sinusoidal current injected to the grid at unity power factor with the average current mode control technique. On the basis of the P&O MPPT algorithm, a power reference for the present insolation level is first calculated. Maintaining this power reference and referring to the AC sine wave of bus bars, a sinusoidal current at unity power factor is injected to the grid. The proportional integral (PI) controller and fuzzy logic controller (FLC) are designed and implemented. The FLC outperforms the PI controller in terms of conversion efficiency and injected power quality. A simulation in the MATLAB/SIMULINK environment is carried out. An experimental prototype is built to validate the proposed idea. The dynamic and steady-state performances of the FLC controller are found to be better than those of the PI controller. The results are presented in this paper.

• 전자공학회논문지A
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• 제33A권4호
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• pp.152-161
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• 1996

In tis work, a three-stage pipelined A/D converter (ADC) was implemented to obtain 10-bit resolution at a conversion rate of 20 msamples/s for video applications. The ADC consists of three identical stages employing a mid-rise coding technique. The interstage errors such as offsets and clock feedthrough are digitally corrected in digitral logic by one overlapped bit between stages. The proposed ADC is optimized by adopting a unit-capacitor array architecture in the MDAC to improve the differential nonlinearity and the yield. Reduced power dissipation has been achieve dby using low-power latched comparators. The prototype was fabricated in a 0.8$\mu$m p-well CMOS technology. The ADC dissipates 160 mW at a 20 MHz clock rate with a 5 V single supply voltage and occupies a die area of 7 mm$^{2}$(2.7 mm $\times$ 2.6mm) including bonding pads and stand-alone internal bias circuit. The typical differential and integral nonlinarities of the prototype are less than $\pm$ 0.6 LSB and $\pm$ 1 LSB, respectively.

• 한국정보통신학회논문지
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• 제15권5호
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• pp.1135-1140
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• 2011

본 논문에서는 버퍼 변환과 단일 위치 레지스터 구조를 이용하여 SDRAM에서의 전력 소모를 줄이는 DTMB 디인터리버 구조를 제안하였다. 수신 성능 향상을 위해 인터리빙의 길이가 긴 DTMB의 디인터리버는 그 특성상 SDRAM에 긴 지연버퍼들을 배치하여 구현한다. 그러나 기존의 구조는 데이터를 읽고 쓸 때 마다 거의 매번 새로운 SDRAM row를 활성화하는 단점이 있다. 제안하는 구조에서는 버퍼 변환을 통해 길이가 짧은 여러 개의 지연버퍼로 변환함으로써 row 활성화 수를 줄이고, 단일 위치 레지스터 구조를 도입하여 위치 레지스터의 개수가 늘어나는 문제점을 보완하였다. 실험결과를 통해 면적은 거의 동일하면서 SDRAM에서의 전력 소모는 약 37%로 줄일 수 있음을 확인하였다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2007년도 제38회 하계학술대회
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• pp.1793-1794
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• 2007

Since it has an advantage of possibility to control using experimentally given coefficient, PID Control is the most widely used method of control in the field of industry. However, since PID controller is not able to reflect the inherent characteristics of individual systems, it needs to be accompanied by additional techniques to supplement. Also, it has disadvantage that it is hard to find a satisfactory coeffi cient when the state of the system's dynamic characteristics and static characteristics are different each other. When the dynamic one shows up, it means the state of system shows a great amount of difference from that of desired such as the moment of beginning control or change of desired state. But, if the state of the system comes close to the desired state, the static characteristics shows up in the system. There are many solutions suggested to overcome problems according to the conversion of two examples of motion shown above. This paper is to confirm PID control's integration ingredient windup phenomenon, and experiment through technique of pre vention of windup actually using PLC(Programmable Logic Co ntroller), and to verify the change in characteristics of control.

• 융합신호처리학회논문지
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• 제12권2호
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• pp.139-144
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• 2011

The modern digital logic technology does not yet satisfy the speed requirements of real-time DSP circuits due to synchronized operation of multiplication and accumulation. This operation degrades DSP performance. Therefore, the double-base number system (DBNS) has emerged in DSP system as an alternative methodology because of fast multiplication and hardware simplicity. In this paper, authors propose a novel multiplication architecture. One operand is an output of a flash analog-to-digital converter (ADC) in DBNS format, while the other operand is a coefficient in the IEEE standard floating-point number format. The DBNS digital output from ADC is produced through a new double base number encoder (DBNE). The multiplied output is in the format of the IEEE standard floating-point number (FPNS). The proposed circuits process multiplication and conversion together. Compared to a typical multiplier that uses the FPNS, the proposed multiplier also consumes 45% less gates, and 44% faster than the FPNS multiplier on Spartan-3 FPGA board. The design is verified with FIR filter applications.

• Spatial Information Research
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• 제23권2호
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• pp.1-9
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• 2015

그래픽 처리 장치(GPU)는 내부에 대량의 산술 논리 연산 장치(ALU)를 보유하고 있다. 대량의 ALU는 병렬 처리를 위해 이용될 수 있으므로, GPU는 효율적인 데이터 처리를 제공한다. 공간 데이터를 지도상에 표현하기 위하여 지리학적 좌표가 필요하다. 좌표들은 측지경도와 측지위도의 형태로 저장된다. 데카르트 좌표계로 구성된 지도를 표현하기 위하여 측지경도와 측지위도는 국제 횡단 메르카토르 좌표계(UTM)로 전환돼야 한다. 좌표계 변환 과정과 변환된 좌표를 화면상에 표현하기 위한 렌더링 과정은 복잡한 부동 소수점 계산이 필요하다. 본 논문에서는 성능 향상을 위해 GPU를 활용한 좌표변환 과정과 렌더링 과정을 병렬적으로 처리하는 기법을 제안한다. 대용량 공간 데이터는 파일로 디스크 내에 저장된다. 대용량 공간 데이터를 효율적으로 처리하기 위하여 공간 데이터 파일들을 하나의 대용량 파일로 병합하고 Memory Mapped File 기법을 활용하여 파일에 접근하는 기법을 제안한다. 본 논문에서는 TIGER/Line 데이터를 활용하여 747,302,971개의 점으로 구성된 공간 데이터의 좌표 변환 및 렌더링 처리 과정을 GPU를 활용하여 병렬로 수행하는 연구를 진행한다. CPU를 이용하여 좌표변환 과정 결과와 렌더링 처리 과정 결과를 비교하여 속도 향상 정도에 대한 결과를 제시한다.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2003년도 ICCAS
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• pp.537-541
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• 2003

In order to control the missiles by aerodynamics, control surfaces sometime called fins are used. Deflection angles of these fins are the right control variables of the aerodynamics, but aerodynamicists prefer to use analytic variables called aileron, elevator and rudder instead of these physical variables, because these three analytic variables dominantly influence on the roll, pitch and yaw channels of the missile maneuver, respectively, and each can be assumed a linear combination of four fin deflection angles. On that basis, roll, pitch and yaw autopilots for controlling the attitudes or lateral acceleration of the missile are designed, and as a consequence outputs of each autopilot are aileron, elevator and rudder commands, respectively. In the existing fin control scheme for the typical tail-fin controlled cruciform missiles, firstly these outputs are distributed to four fin defection commands, and after that four fins are actuated by fin controllers so that their deflections follow the commands. This paper shows that performance of such control schemes can be degraded significantly when fin actuators have certain physical constraints such as slew rate, voltage or current limit, uncertainty of actuator dynamics, and so on, and propose a new control scheme which alleviates such problems. This scheme can be widely applied to various fin actuation systems. But in this paper, for convenience, tail-fin controlled cruciform missile is taken as an example, and it is shown that a proposed control scheme gives better performance than the existing one.

• 한국자동차공학회논문집
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• 제24권3호
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• pp.302-309
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• 2016

Urea-SCR system is currently regarded as promising NOx reduction technology for diesel engines. SCR system has to achieve maximal NOx conversion in combination with minimal $NH_3$ slip. In this study, model based open loop control for urea injection was developed and assessed in the European Transient Cycle (ETC) for heavy duty diesel engine. On the basis of the transient modeling, the kinetic parameters of the $NH_3$ adsorption and desorption are calibrated with the experimental results performed over the zeolite based catalyst. $NH_3$ storage or surface coverage of SCR catalyst can not be measured directly and has to be calculated, which is taken into account as a control parameter in this model. In order to reduce $NH_3$ slip while maintaining NOx reduction, $NH_3$ storage control algorithm was applied to correct the basic urea quantity. If the actual $NH_3$ surface coverage is higher than the maximal $NH_3$ surface coverage, the urea injection quantity is significantly reduced in the ETC cycle. By applying this logic, the resulting $NH_3$ slip peak can be avoided effectively. With optimizing the kinetic parameters based on standard SCR reaction, it suggests that a simplified, less accurate model can be effective to evaluate the capability of model based control in the ETC cycle.

• 제어로봇시스템학회논문지
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• 제14권7호
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• pp.711-719
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• 2008

Although non-real time simulation and pilot based evaluations are available for the development of flight control computer prior to real flight tests, there are still many risky factors. The control law designed for prototype aircraft often leads to degraded performance from the initial design objectives, therefore, the proper evaluation methods should be applied such that flight control law designed can be verified in real flight environment. The one proposed in this paper is IFS(In-Flight Simulator). Currently, this system has been implemented into the F-18 HARV(High Angle of Attack Research Vehicle), SU-27 and F-16 VISTA(Variable stability. In flight Simulation Test Aircraft) programs. This paper addresses the concept of switching mechanism for FLCC(Flight Control Computer)-SWMC(Switching Mechanism Computer) using 1553B communication based on flight control law of advanced supersonic trainer. And, the fader logic of TFS(Transient Free Switch) and stand-by mode of reset '0' type are designed to reduce abrupt transient and minimize the integrator effect in pitch axis control law. It hans been turned out from the pilot evaluation in real time that the aircraft is controllable during the inter-conversion process through the flight control computer, and level 1 handling qualities are guaranteed. In addition, flight safety is maintained with an acceptable transient response during aggressive maneuver performed in severe flight conditions.