1 |
Minh Son Nguyen, Insoo Kim, Kyusun Choi and Jongsoo Kim, Design and Implementation of Flash ADC and DBNS FIR filter integrated on DSP System, ISOCC'09, vol.1, Nov 2009, pp. 430-435.
|
2 |
Minh Son Nguyen, Insoo Kim, Jae ha Choi and Jongsoo Kim, Algorithm and Design of Double-base Log Encoder for Flash A/D Converters, KISPS, vol. 10, Nov 2009, pp. 289-293.
|
3 |
Daegyu Lee, Jincheol Yoo, Kyusun Choi, Design Method and Automation of Comparator Generation for Flash A/D Converter, ISQED, 2002, pp. 138 - 142.
|
4 |
Jaehyun Lim, Insoo Kim, Nguyen Minh Son, Jincheol Yoo, Jongsoo Kim and Kyusun Choi, Low Power Flash A/D Converter with TIQ Comparators for Multi-Standard Mobile Applications, IREE, vol 4, Dec 2009, pp. 1447 -1452.
|
5 |
Daegyu Lee, Jincheol Yoo, Kyusun Choi and Jahan Ghaznavi, Fat Tree Encoder Design for Ultra-High Speed Flash A/D Converters, The 45th Midwest Symposium on Circuits and Systems, vol.2, Aug 2002, pp. 87 90.
|
6 |
Jincheol Yoo, A TIQ Based CMOS Flash A/D Converter for SoC Applications, Ph.D. Dissertation, Dept. of Comp. Sci. and Eng. The Pennsylvania State University, 2003.
|
7 |
Sheng-Chien Huang and Liang-Gee Chen, A 32-bit Logarithmic Number System Processor, Journal of VLSI Signal Processing, vol 14, 1996, pp. 311 - 319.
DOI
ScienceOn
|
8 |
Suganth Paul, Nikhil Jayakurnar, and Sunil P. Khatri, A Fast Hardware Approach for Approximate, Efficient Logarithm and Antilogarithm Computations, IEEE Tran. on VLSI, vol 17, Feb. 2009, pp. 269-277.
DOI
|
9 |
K. Johansson, O. Gustafson, and L. Wanhammar, Implementation of elementary functions for logarithmic number systems, IET Comput. Digit. . Tech., vol. 2, Jul. 2008, pp. 295-304.
DOI
ScienceOn
|
10 |
Tso-Bing Juang, Sheng-Hung Chen, and Huang-Jia Cheng, A Lower Error and ROM-Free Logarithmic Converter for Digital Signal Processing Applications, IEEE Tran. on Circuit and Systems, vol 56 Dec. 2009, pp. 931-935.
|
11 |
Huey Ling, High-Speed Binary Adder, IBM Journal of Research and Development, vol.5-3, 1981.
|
12 |
Minh Son Nguyen and jongsoo Kim, The Conversion Algorithm between Double-Base Number System and Floating-Point Number System applied for FIR filter, The 24th ITC-CSCC 2009, May 2009, pp 1458-1461.
|
13 |
Mustafa GOK, A Novel IEEE Rounding Algorithm for High-speed Floating-point Multipliers, The VLSI journal, 2007, pp. 549 - 560.
|
14 |
Bhaskar D. Rao, Floating-point Arithmetic and Digital filter, IEEE Tran. on Signal Processing, vol 40, 1992, pp. 85-95.
DOI
ScienceOn
|
15 |
Christian Piguet, Low-Power CMOS Circuit: Technology, Logic Design and CAD tools, Taylor & Fracis, 2006.
|
16 |
Kacem, R.; Khouja, N.; Grati, K; Ghazel, A., Low Power Implementation of Digital Filters using DBNS Representation and Sub-expression Sharing, The 2nd International Conference on Signals, Circuits and Systems, Nov 2008, pp. 1-6.
|
17 |
Vassil S. Dimitrov, Graham A. JUllien, and W. C. Miller, Theory and Applications of the Double-Base Number System, IEEE Tran. on Computers, vol. 48, 1999, pp. 1098 - 1106.
DOI
ScienceOn
|
18 |
Vassil S. Dimitrov and Graham A. jullien, A New Number Representation with Applications, IEEE Circuits and Systems Magazine, 2003.
|
19 |
Walt Kester, Mixed-Signal and DSP Design Techniques, Analog Devices, 2003.
|
20 |
Roberto Muscedere , Vassil Dimitrov , Graham A. Jullien , William C. Miller, Efficient Techniques for Binary to Multidigit Multidimensional Logarithmic Number System Conversion Using Range Addressable Look-Up Tables, IEEE Tran. on Computers, vol. 54-3, March 2005, pp, 257 - 271.
DOI
ScienceOn
|
21 |
Amitabha, Kolkata, Pavel Sinha, Kenneth Alan Newton, Krishanu Mulherjee, Triple-Base Number Digital Signal and Numerical Processing System, US Patent, Jan 24, 2008.
|