[KSCI] Korea Science Citation Index Service

A New Multiplication Architecture for DSP Applications

Son, Nguyen-Minh (University of Ulsan)
Kim, Jong-Soo (School of Eleetrical Engineering, University of Ulsan)
Choi, Jae-Ha (School of Electrical Engineering, University of Ulsan)

Publication Information

Journal of the Institute of Convergence Signal Processing / v.12, no.2, 2011 , pp. 139-144 More about this Journal

Abstract

The modern digital logic technology does not yet satisfy the speed requirements of real-time DSP circuits due to synchronized operation of multiplication and accumulation. This operation degrades DSP performance. Therefore, the double-base number system (DBNS) has emerged in DSP system as an alternative methodology because of fast multiplication and hardware simplicity. In this paper, authors propose a novel multiplication architecture. One operand is an output of a flash analog-to-digital converter (ADC) in DBNS format, while the other operand is a coefficient in the IEEE standard floating-point number format. The DBNS digital output from ADC is produced through a new double base number encoder (DBNE). The multiplied output is in the format of the IEEE standard floating-point number (FPNS). The proposed circuits process multiplication and conversion together. Compared to a typical multiplier that uses the FPNS, the proposed multiplier also consumes 45% less gates, and 44% faster than the FPNS multiplier on Spartan-3 FPGA board. The design is verified with FIR filter applications.

Keywords

Double-base Number System; flash ADC; double-base number encoder; logarithm number system; DSP; FIR filter;

Citations & Related Records

Times Cited By KSCI : 1 (Citation Analysis)

Reference
Cited By KSCI

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