• Journal of Aerospace System Engineering
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• v.15 no.5
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• pp.98-105
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• 2021

This study presented the results of the static load tests conducted to verify the structural robustness of the composite oxidant tank for a space launch vehicle. First, we introduced the test equipment used in the static load test of the composite oxidant tank, and then described the test requirements that the composite oxidant tank must satisfy. In addition, we presented a test set-up diagram consisting of the static load test fixture, hydraulic pressure, control equipment, and data acquisition equipment, and the load profile of the static load test of the composite oxidant tank consisting of shear, equivalent compression, bending, and combination tests. As a result of load control, we verified the reliability of this test by showing the errors between the input load and the feedback load in each channel according to the increase of the test load, and the feedback error between the channel A and channel B of load cell in each load actuator. As a result of the static load test, the load of the actuator was properly controlled within the allowable error range in each test, and we found that the test specimen did not cause damage or buckling that causes significant structural defects in the required load.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.7
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• pp.1237-1245
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• 2006

This paper presented a hardware implementation of ARIA, which is a Korean standard l28-bit block cryptography algorithm. In this work, ARIA was designed technology-independently for application such as ASIC or core-based designs. ARIA algorithm was fitted in FPGA without additional components of hardware or software. It was confirmed that the rate of resource usage is about 19% in Altera EPXAl0F1020CI and the resulting design operates stably in a clock frequency of 36.35MHz, whose encryption/decryption rate was 310.3Mbps. Consequently, the proposed hardware implementation of ARIA is expected to have a lot of application fields which need high speed process such as electronic commerce, mobile communication, network security and the fields requiring lots of data storing where many users need processing large amount of data simultaneously.

• Transactions of the KSME C: Technology and Education
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• v.3 no.4
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• pp.265-271
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• 2015

The bonding process should be achieved in vacuum environment to avoid air bubble. In this study, we studied about pressure uniformity that became an issue in thermo compression bonding usually. Uniform press is realized by the method that use air spring and metal form spring. The concept of uniform press using air spring is removed except pressing direction in the press processing so angle between the vector of pressure surface and the pressure axis is parallel automatically. Air spring compensate the errors of machining and assembly. Metal form compensate the thermal deformation and flatness error.

• Journal of Korea Multimedia Society
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• v.11 no.2
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• pp.163-174
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• 2008

The H.264/AVC provides gains in compression efficiency of up to 50% over a wide range of bit rates and video resolutions compared to previous standards. However, to achieve such high coding efficiency, the complexity of H.264/AVC encoder is also increased drastically than previous ones, mainly because of mode decision. In this paper, we propose a three-step mode decision algorithm for fast encoding in H.264/AVC. In the first step, we select skip mode or inter mode by considering the temporal correlation and spatial correlation. In the second step, if the result of the first step is INTER mode, we select one group between two groups for final mode. In the third step, we select final mode by exploiting the pixel values of error macroblock or the modes of adjacent macroblocks. Simulations show that the proposed method reduces the encoding time by 42% on average without any significant PSNR losses.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.12
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• pp.56-65
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• 2001

This paper proposes an algorithm for the capacitance extraction of general 3-dimensional conductors in an ideal uniform dielectric that uses a high-order quadrature approximation method combined with the typical first-order collocation method to enhance the accuracy and adopts an efficient matrix-vector product algorithm for the model-order reduction to achieve efficiency. The proposed method enhances the accuracy using the quadrature method for interconnects containing corners and vias that concentrate the charge density. It also achieves the efficiency by reducing the model order using the fact that large parts of system matrices are of numerically low rank. This technique combines an SVD-based algorithm for the compression of rank-deficient matrices and Gram-Schmidt algorithm of a Krylov-subspace iterative technique for the rapid multiplication of matrices. It is shown through the performance evaluation procedure that the combination of these two techniques leads to a more efficient algorithm than Gaussian elimination or other standard iterative schemes within a given error tolerance.

• Journal of the Korean Society of Fisheries and Ocean Technology
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• v.56 no.3
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• pp.230-237
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• 2020

In order to design a diesel engine system and predict its performance, it is necessary to analyze the gas flow of the intake and exhaust system. A gas flow analysis in three-dimensional (3D) format needs a high-resolution workstation and enormous time for analysis. Therefore, the method of characteristics (MOC) was used for a gas flow analysis with a fast calculation time and a low-resolution workstation. An experiment was conducted on a single cylinder diesel engine to measure pressure in cylinder, intake pipe and exhaust pipe. The one-dimensional (1D) gas flow was analyzed under the same conditions as the experiment. The engine speed, valve timing and compression ratio were the same conditions and the intake pressure was inputted as the experimental results. Bent pipe such as an exhaust port that cannot be realized in 1D was omitted. As results of validation, the cylinder pressure showed accuracy, but the exhaust pipe pressure exhibited inaccuracy. This is considered as an error caused by the failure to implement a bent pipe such as an exhaust port. When analyzed in 3D, calculation time required 61 hours more based on a model of this study. In the future, we intend to implement a bent pipe that cannot be realized in 1D using 3D and prepare a method to supplement reliability by using 1D-3D coupling.

• Journal of Korea Society of Industrial Information Systems
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• v.22 no.5
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• pp.17-24
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• 2017

Recently Deep-learning, Technologies using Large or Deep Artificial Neural Networks, have Shown Remarkable Performance, and the Increasing Size of the Network Contributes to its Performance Improvement. However, the Increase in the Size of the Neural Network Leads to an Increase in the Calculation Amount, which Causes Problems Such as Circuit Complexity, Price, Heat Generation, and Real-time Restriction. In This Paper, We Propose and Test a Method to Reduce the Number of Network Connections by Effectively Pruning the Redundancy in the Connection and Showing the Difference between the Performance and the Desired Range of the Original Neural Network. In Particular, we Proposed a Simple Method to Improve the Performance by Re-learning and to Guarantee the Desired Performance by Allocating the Error Rate per Layer in Order to Consider the Difference of each Layer. Experiments have been Performed on a Typical Neural Network Structure such as FCN (full connection network) and CNN (convolution neural network) Structure and Confirmed that the Performance Similar to that of the Original Neural Network can be Obtained by Only about 1/10 Connection.

• Journal of the Institute of Convergence Signal Processing
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• v.9 no.4
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• pp.321-328
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• 2008

In this paper, we propose the hardware architecture of two-dimensional discrete wavelet transform (2D DWT) and quantization for using JPEG2000. Color 2-D DWT processor is proposed that is to apply to JPEG 2000 Hard-wired Encoder. JPEG 2000 DWT processor uses the Daubechies' (9,7) bi-orthogonal filter, and we design by minimizing error of the DWT transformer by ${\pm}1$ LSB during compression and decompression. We designed the DWT filters that using by using shift and adder structure instead of multiplier structure which raise the hardware complexity. It is improve the operation speed of filters and reduce the hardware complexity. The proposed system is designed by the hardware description language Verilog-HDL and verified by Synopsys Design Analyzer using TSMC 0.25${\mu}m$ ASIC library.

• Journal of Korea Multimedia Society
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• v.11 no.11
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• pp.1480-1490
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• 2008

Design of a linear predictor and matching of an entropy coder is the art of lossless audio coding. In this paper, we use the covariance method and the Choleskey decomposition for calculating linear prediction coefficients instead of the autocorreation method and the Levinson-Durbin recursion. These results are compared to the polynomial predictor. Both of them, the predictor which has small prediction error is selected. For the entropy coding, we use the Golomb-Rice coder using the block-based parameter estimation method and the sequential adaptation method with LOCO-land RLGR. The proposed predictor and the block-based parameter estimation have $2.2879%{\sim}0.3413%$ improved compression ratios compared to FLAC lossless audio coder which use the autocorrelation method and the Levinson-Durbin recursion. The proposed predictor and the LOCO-I adaptation method could improved by $2.2879%{\sim}0.3413%$. But the proposed predictor and the RLGR adaptation method got better results with specific signals.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.3
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• pp.585-593
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• 2017

In this paper, we propose a deblocking filter hardware architecture for low-power HEVC (High-Efficiency Video Coding) in-loop for mobile systems. HEVC performs image compression on a block-by-block basis, resulting in blockage of the image due to quantization error. The deblocking filter is used to remove the blocking phenomenon in the image. Currently, UHD video service is supported in various mobile systems, but power consumption is high. The proposed low-power deblocking filter hardware structure minimizes the power consumption by blocking the clock to the internal module when the filter is not applied. It also has four parallel filter structures for high throughput at low operating frequencies and each filter is implemented in a four-stage pipeline. The proposed deblocking filter hardware structure is designed with Verilog HDL and synthesized using TSMC 65nm CMOS standard cell library, resulting in about 52.13K gates. In addition, real-time processing of 8K@84fps video is possible at 110MHz operating frequency, and operation power is 6.7mW.