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Error Recovery Schemes with IPv6 Header Compression  

Ha Joon-Soo (광운대학교 전자재료공학과 디지털 설계 및 테스트 연구실)
Choi Hyun-Jun (광운대학교 전자재료공학과 디지털 설계 및 테스트 연구실)
Seo Young-Ho (한성대학교 정보통신공학과)
Kim Dong-Wook (광운대학교 전자재료공학과 디지털 설계 및 테스트 연구실)
Publication Information
Journal of the Korea Institute of Information and Communication Engineering / v.10, no.7, 2006 , pp. 1237-1245 More about this Journal
Abstract
This paper presented a hardware implementation of ARIA, which is a Korean standard l28-bit block cryptography algorithm. In this work, ARIA was designed technology-independently for application such as ASIC or core-based designs. ARIA algorithm was fitted in FPGA without additional components of hardware or software. It was confirmed that the rate of resource usage is about 19% in Altera EPXAl0F1020CI and the resulting design operates stably in a clock frequency of 36.35MHz, whose encryption/decryption rate was 310.3Mbps. Consequently, the proposed hardware implementation of ARIA is expected to have a lot of application fields which need high speed process such as electronic commerce, mobile communication, network security and the fields requiring lots of data storing where many users need processing large amount of data simultaneously.
Keywords
Cryptography; ARIA; FPGA; VLSI;
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
연도 인용수 순위
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