• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.467-468
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• 2008

In this paper, a logic family, the transmission gate CMOS(TG CMOS) is proposed, which combines the transmission gate and pass transistor resulting in a different configuration from traditional full CMOS. In the simulation, basic cells comprising this logic are designed and their dynamic responses are analyzed. The simulation shows their performance is exceeding that of conventional full CMOS.

• Proceedings of the KIEE Conference
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• 2003.07d
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• pp.2155-2157
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• 2003

본 논문에서는 동일동기화(Identical Synchronization)파 일반동기화(General Synchronization)를 이용한 하이퍼카오스 시스템을 구성하고 검증하였다. 단일 카오스 모듈을 이용한 통신은 많은 보안의 취약점을 가진 것으로 알려져 있다. 이에 이런 취약점을 보안하기 위해 여러 방법들이 도입되었다. 본 논문은 두 개의 2-double scroll Chua 회로와 두 개의 2-double scroll Chua 오실레이터를 이용하여 하이퍼카오스 회로의 송수신단을 구성하고 동기화 방법을 제안하였다.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.78-81
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• 2002

We propose a current-mode analog programmable finite-impulse-response (FIR) filter with variable tap circuits. From the circuit simulation, the operation of the 7- tap FIR filter is confirmed. We design and fabricate the 0.0625-step tap circuit using 0.8$\mu\textrm{m}$ CMOS technology. The proposed FIR filter has a variable length of taps and variable coefficients, so it has a potential for being used to software defined radio (SDR) terminals.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.6
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• pp.562-568
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• 2013

This paper presents a design of a wireless power transfer system based on magnetic resonant coupling technology with in-band wireless communication. To increase the transmission distance and compensate for the change in the effective capacitance due to the varying distance, the proposed system used a loop antenna with a selectable capacitor array. Because the increased transmission distance enables multiple charging, we added a communication protocol operated at the same frequency band to manage a network and control power circuits. In order to achieve the efficient bandwidth in both power transfer mode and communication mode, the S-parameters of the loop antennas are adjusted by switching a series resistor. Our test results showed that the loop antenna achieved a high Q factor in power transfer mode and enough passband in communication mode.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.9
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• pp.259-269
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• 2012

With the lower supply voltage and the higher operating frequency in integrated circuits, the analysis of the power distribution network (PDN) including on-chip inductances becomes more important. In this paper, an effective inductance extraction method for a regular on-chip power grid structure is proposed. The loop inductance model applicable to chip layout is proposed and the inductance extraction tool using the proposed inductance model based on post layout RC circuits is developed. The accuracy of the proposed loop model and the developed tool is verified by comparing the test circuit simulation results with those from the partial element equivalent circuit (PEEC) model. The voltage fluctuation from the RLC circuits extracted by the developed tool was examined for the analysis of on-chip inductance effects. The significance of on-chip power grid inductance was investigated by the co-simulation of chip-package-PCB.

• The Journal of the Korea institute of electronic communication sciences
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• v.10 no.8
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• pp.921-926
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• 2015

For the over-heat protection purpose in power strip devices, over-current detection/protection circuits, such as bimetal, switching circuit, and microprocessor-based relay circuit, have been widely setup in high-end products. Most of these circuits are connected to the power line in parallel and, thus, they are sensitive to the line voltage and current distortion. Moreover, these protection circuits are often costly and, therefore, it is hard to meet the commercial requirements. A low-cost over-current detection circuit with the contactless current transducer is designed and tested in this paper. The detection circuit is galvanically isolated from the power line and, thus, less sensitive to the line voltage distortion. The experimental results show that the proposed circuit accurately operates despite of its simple structure and low-cost electronic parts.

• The Journal of the Korea institute of electronic communication sciences
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• v.9 no.4
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• pp.447-454
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• 2014

Recently most of functional synthesis methods for quantum circuit realization have a tendency to adopt the declarative functional expression more suitable for computer algorithms, so it's difficult to analysis synthesized quantum functions. This paper presents a new functional representation of quantum circuits compatible with simple architecture and intuitive thinking. The proposal of this paper is a new functional synthesis development by using the control functions as the power of corresponding to affine-controlled quantum gates based on the mathematical substitution of serial-product matrix operation over the target line for the arithmetic and modulo-2 ones between power functions of unitary operators. The functional synthesis algorithm proposed in this paper is useful for the functional expressions and synthesis using both of reversible and irreversible affine-controlled NCV-quantum gates.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.3 no.2
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• pp.329-337
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• 1999

In this dissertation, the characteristics of W-CDMA(Wideband CDMA) are studied and required specifications of IMT-2000 transceiver using W-CDMA method are proposed. Also, in order to design the RF circuits satisfied the proposed specifications, theoretical models are expanded and real circuits are made. Then the RF circuits of the mobile stations are implemented in the three parts, transmitter, receiver and frequency synthesizer and are evaluated. The frequency synthesizer is designed using techniques of swallow counter and passive 3rd loop filter. For improving characteristics of the loop, a LPF was added to the 2nd loop filter. So although the locking times are loosed, the spurious are reduced. The output power of transmitter is over 50mW, the spurious output is -40dB/30kHz at 5MHz offset and power control range is -20dB at 2.5V. The proposed specifications are considered in highly practical environment and the theoretical designs and the experiments are expressed as simply as possible in order to facilitate understanding. It stands to reason that the results of this study can be used to design the wider CDMA(25MHz Bandwidth) mobile communication systems.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.11
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• pp.57-65
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• 2014

This paper presents a framework that is based on a reconfigurable macro-model of current-mode logic (CML) high-speed digital circuits enabling equation-based design optimization. The proposed macro-model is compatible with geometric programming, thereby enabling constraint-driven top-level power optimization. The proposed optimization framework is applied to a design of CML based serial-link transmitter with user-defined design specifications as an example of high speed digital circuits using 45nm and 90nm CMOS technology. The proposed optimization framework can derive a design with optimal power efficiency for given transistor technology nodes.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.10
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• pp.917-925
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• 2016

Schmitt Trigger logic is a gate level design method to have hysteresis characteristics to improve noise immunity in digital circuits. Dynamic Threshold voltage MOS(DTMOS) Schmitt trigger circuits can improve noise immunity without adding additional transistors but by controlling substrate bias. The performance of DTMOS Schmitt trigger logic has not been verified yet in standard CMOS process through measurement. In this paper, DTMOS Schmitt trigger logic was implemented and verified using Magna $0.18{\mu}m$ MPW process. DTMOS Schmitt trigger buffer, inverter, NAND, NOR and simple digital logic circuits were made for our verification. Hysteresis characteristics, power consumption, and delay were measured and compared with common CMOS logic gates. EM Immunity enhancement was verified through Direct Power Injection(DPI) noise immunity test method. DTMOS Schmitt trigger logics fabricated using CMOS process showed a significantly improved EM Immunity in 10 M~1 GHz frequency range.