• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.7
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• pp.122-129
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• 2014

Due to remarkable market growth of smart devices, higher performance and more functionalities are required for a core system-on-chip (SoC), and thus the power demand is rapidly increasing. However, aggressive shrink of CMOS transistor have brought severe process variations thereby adversely affected the performance and power consumption under strict power constraint. Voltage binning (VB) scheme is one of the effective post silicon tuning techniques, which can reduce parametric yield loss due to process variations by adjusting supply voltage. In this paper, an optimal supply voltage tuning based voltage binning technique is proposed to reduce average power without an additional yield loss. Considering the different LVCC margins of process corners along with speed and leakage characteristics, the proposed method can optimize the deviation of voltage margin and thus save power consumption. When applying on a 30nm mobile SoC product, the experimental results showed that the proposed technique reduced average power consumption up to 6.8% compared to traditional voltage binning under the same conditions.

• Journal of IKEEE
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• v.7 no.2 s.13
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• pp.245-252
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• 2003

We designed a silicon pressure sensor interface circuit with digital calibration capability. The interface circuit is composed of an analog section and a digital section. The analog section amplifies the weak signal from the sensor and the digital section handles the calibration function and communication function between the chip and outside microcontroller that controls the calibration. The digital section is composed of I2C serial interface, memory, trimming register and controller. The I2C serial interface is optimized to suit the need of on-chip silicon microsensor in terms of number of IO pins and silicon area. The major part of the design is to build a controller circuit that implements the optimized I2C protocol. The designed chip was fabricated through IDEC's MPW. We also made a test board and the test result showed that the chip performs the digital calibration function very well as expected.

• Journal of IKEEE
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• v.15 no.4
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• pp.330-338
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• 2011

In this paper, a current-mode buck-boost converter using Multiple switching devices is presented. The efficiency of the proposed converter is higher than that of conventional buck-boost converter. In order to improve the power efficiency at the high current level, the proposed converter is controlled with PWM(pulse width modulation) method. The converter has maximum output current 300mA, input voltage 3.3V, output voltage from 700mV to 12V, 1.5MHz oscillation frequency, and maximum efficiency 90%. Moreover, this paper proposes watchdog circuits in order to ensure the reliability and to improve the performance of dc-dc converters. An electrostatic discharge(ESD) protection circuit for deep submicron CMOS technology is presented. The proposed circuit has low triggering voltage using gate-substrate biasing techniques. Simulated result shows that the proposed ESD protection circuit has lower triggering voltage(4.1V) than that of conventional ggNMOS(8.2V).

• Journal of IKEEE
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• v.17 no.1
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• pp.77-82
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• 2013

In this paper, dc-dc buck converter controled by the peak current-mode pulse-width-modulation (PWM) presented. Based on the small-signal model, we propose the novel methods of the power stage and the systematic stability designs. To improve the reliability and performance, over-temperature and over-current protection circuits have been designed in the dc-dc converter systems. To prevent electrostatic An electrostatic discharge (ESD) protection circuit is proposed. The proposed dc-dc converter circuit exhibits low triggering voltage by using the gate-substrate biasing techniques. Throughout the circuit simulation, it confirms that the proposed ESD protection circuit has lower triggering voltage(4.1V) than that of conventional ggNMOS (8.2V). The circuit simulation is performed by Mathlab and HSPICE programs utilizing the 0.35um BCD (Bipolar-CMOS-DMOS) process parameters.

• Journal of IKEEE
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• v.21 no.1
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• pp.66-69
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• 2017

In recent year, energy harvesting technologies from the ambient environments such as light, motion, wireless waves, and temperature again a lot of attraction form research community [1-5] due to its efficient solution in order to substitute for conventional power delivery methods, especially in wearable together with on-body applications. The drawbacks of battery-powered characteristic used in commodity applications lead to self-powered, long-lifetime circuit design. Thermoelectric generator, a solid-state sensor, is useful compared to the harvesting devices in order to enable self-sustained low-power applications. TEG based on the Seebeck effect is utilized to transfer thermal energy which is available with a temperature gradient into useful electrical energy. Depending on the temperature difference between two sides, amount of output power will be proportionally delivered. In this work, we illustrated a low-input voltage energy harvesting circuit applied discontinuous conduction mode (DCM) method for getting an adequate amount of energy from thermoelectric generator (TEG) for a specific wearable application. With a small temperature gradient harvested from human skin, the input voltage from the transducer is as low as 60mV, the proposed circuit, fabricated in a $0.6{\mu}m$ CMOS process, is capable of generating a regulated output voltage of 4.2V with an output power reaching to $40{\mu}W$. The proposed circuit is useful for powering energy to battery-less systems, such as wearable application devices.

• International Journal of Internet, Broadcasting and Communication
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• v.7 no.1
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• pp.15-19
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• 2015

The depth information of an image is used in a variety of applications including 2D/3D conversion, multi-view extraction, modeling, depth keying, etc. There are various methods to acquire depth information, such as the method to use a stereo camera, the method to use the depth camera of flight time (TOF) method, the method to use 3D modeling software, the method to use 3D scanner and the method to use a structured light just like Microsoft's Kinect. In particular, the depth camera of TOF method measures the distance using infrared light, whereas TOF sensor depends on the sensitivity of optical light of an image sensor (CCD/CMOS). Thus, it is mandatory for the existing image sensors to get an infrared light image by bundling several pixels; these requirements generate a phenomenon to reduce the resolution of an image. This thesis proposed a measure to acquire a high-resolution image through gradual area movement while acquiring a low-resolution image through pixel bundling method. From this measure, one can obtain an effect of acquiring image information in which illumination intensity (lux) and resolution were improved without increasing the performance of an image sensor since the image resolution is not improved as resolving a low-illumination intensity (lux) in accordance with the gradual pixel bundling algorithm.

• Proceedings of the Materials Research Society of Korea Conference
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• 2009.05a
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• pp.22.2-22.2
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• 2009

Currently, metal silicides become increasingly more essential part as a contact material in complimentary metal-oxide-semiconductor (CMOS). Among various silicides, NiSi has several advantages such as low resistivity against narrow line width and low Si consumption. Generally, metal silicides are formed through physical vapor deposition (PVD) of metal film, followed by annealing. Nanoscale devices require formation of contact in the inside of deep contact holes, especially for memory device. However, PVD may suffer from poor conformality in deep contact holes. Therefore, Atomic layer deposition (ALD) can be a promising method since it can produce thin films with excellent conformality and atomic scale thickness controllability through the self-saturated surface reaction. In this study, Ni thin films were deposited by thermal ALD using bis(dimethylamino-2-methyl-2-butoxo)nickel [Ni(dmamb)2] as a precursor and NH3 gas as a reactant. The Ni ALD produced pure metallic Ni films with low resistivity of 25 $\mu{\Omega}cm$. In addition, it showed the excellent conformality in nanoscale contact holes as well as on Si nanowires. Meanwhile, the Ni ALD was applied to area-selective ALD using octadecyltrichlorosilane (OTS) self-assembled monolayer as a blocking layer. Due to the differences of the nucleation on OTS modified surfaces toward ALD reaction, ALD Ni films were selectively deposited on un-coated OTS region, producing 3 ${\mu}m$-width Ni line patterns without expensive patterning process.

• Journal of the Korean Vacuum Society
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• v.19 no.2
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• pp.141-147
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• 2010

In this study, high-k oxide films like $Al_2O_3$, $TiO_2$, $HfO_2$ were deposited on Si, $SiO_2$/Si, GaAs wafers, and then the thermal conductivity was measured by using thermo-reflectance method which utilizes the reflectance variation of the film surface produced by the periodic temperature variation. The result shows that high-k oxide films with 50 nm thickness have high thermal conductivity of 0.80~1.29 W/(mK). Therefore, effectively dissipate the heat generated in the electric circuit such as CMOS memory device, and the heat transfer changes according to the micro grain size.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.40 no.2
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• pp.390-396
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• 2015

The drastic growth of mobile communication and spreading of smart phone make the significant attention on Location Based Service. The one of most important things for vitalizations of LBS is the accurate estimating position for mobile object. Focusing on an image sensor deployed in smart phone, we develop a LED based positioning estimation framework. The developed approaches can strengthen the advantages of independent indoor applicability of LED. The estimation of LED based positioning is effectively applied to any indoor environment. We put a focus especially on the algorithmic framework. of image processing of smart phone. From LED lighting, we can obtain a typical signal image which contains the unique positioning information. Furthermore test-bed based on smart phone platform is practically developed and all data have been harvested from the actual measurement of test indoor area. This can approve the practical usefulness of proposed framework.

• The Journal of the Korea institute of electronic communication sciences
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• v.13 no.4
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• pp.721-728
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• 2018

This paper introduces various linear block error correction code and compares performances of the correction circuits. As the risk of errors due to power noise has increased, ECC(: Error Correction Code) has been introduced to prevent the bit error. There are two representatives of ECC structures which are SEC-DED(: Single Error Correction Double Error Detection) and SEC-DED-DAEC(: Double Adjacent Error Correction). According to simulation results, the SEC-DED circuit has advantages of small area and short delay time compared to SEC-DED-DAEC circuits. In case of SED-DED-DAEC, there is no big difference between Dutta's and Pedro's from performance point of view. Therefore, Pedro's code is more efficient than Dutta' code since the correction rate of Pedro's code is higher than that of Dutta's code.