• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.2 s.332
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• pp.23-30
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• 2005

This paper describes a DLL(delay locked loop)-based multi-clock generator having the lower active stand-by power as well as a fast relocking after re-activating the DLL. for low power and high speed VLSI chip. It enables a frequency multiplication using frequency multiplier scheme and produces output clocks with 50:50 duty-ratio regardless of the duty-ratio of system clock. Also, digital control scheme using DAC enables a fast relocking operation after exiting a standby-mode of the clock system which was obtained by storing analog locking information as digital codes in a register block. Also, for a clock multiplication, it has a feed-forward duty correction scheme using multiphase and phase mixing corrects a duty-error of system clock without requiring additional time. In this paper, the proposed DLL-based multi-clock generator can provides a synchronous clock to an external clock for I/O data communications and multiple clocks of slow and high speed operations for various IPs. The proposed DLL-based multi-clock generator was designed by the area of $1796{\mu}m\times654{\mu}m$ using $0.35-{\mu}m$ CMOS process and has $75MHz\~550MHz$ lock-range and maximum multiplication frequency of 800 MHz below 20psec static skew at 2.3v supply voltage.

• Proceedings of the KIEE Conference
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• 2006.10c
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• pp.385-387
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• 2006

We made the logic that can transmit the service data and clock of interest by using the optical signal and demodulate the original signal at the receiving end. Because We can interface the all communications equipment to which We intended to send the signal. We can modulate the dock and clocked data using optical signal and then transmit the original optical signal to the receiving end, finally, arbitrarily control the traffic between ports.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.277-280
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• 2001

The proposed clock generator lowers the operating frequency in a system core though it keeps data bandwidth high because it has a multiphase clocking architecture. Moreover. it has a dual loop which is comprised of an inner analog phase generation loop and outer digital phase control loop. It has both advantages of DLL's wide operating range and DLL's low jitter The proposed design has been demonstrated in terms of the concept and Hspice simulation. All circuits were designed using a 0.25${\mu}{\textrm}{m}$ CMOS process and simulated with 2.5 V power supply.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.733-736
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• 1999

In this Paper, Bit selectable and Bi-directional Interface Port is described, which can communicate data with the peripheral devices. Specially A description of the asynchronous design method is given to remove the clock skew phenomenon and the output asynchronous control method which finds the optimal clock and controls all the enable signal of the output pins at the same time is presented. Using this technique interface ports have delay time of less-than 0.5㎱.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.839-842
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• 1998

The wide spread of multimedia system demands a large viewin gdesply device which can inform a message to many peoples in open area. This paper is about the design, simulating and testing of a large viewing LED pannel control ASIC(application specific integrated circuit). This LED pannel control ASIC runs on 16 bit microprocessor MC68EC000 and has following functions:16 line interlaced LED pannel controller, memory controller, 16 channel priority inerrupt controller, 2 channel direct memory access controller, 2 channel 12 bit clock and timer, 2 channel infrared remocon receiver, 2 channel RS-232C with 16byte FIFO, IBM PC/AT compatible keyboard interface, battery backuped real time clock, ISA bus controller, battery backuped 256 byte SRAM and watech dog timer. The 0.6micron CMOS sea of gate is used to design the ASIC in amount of about 39,000 gates.

• Journal of Korea Society of Digital Industry and Information Management
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• v.9 no.3
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• pp.67-78
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• 2013

In this paper, We proposed an development method of application framework for using the precision time protocol(PTP) based on physical layer devices to synchronize clocks across a network with IEEE1588 capable devices. The algorithm was not designed as a complete solution across all conditions, but is intended to show the feasibility of such a for the PTP(Precision Time Protocol) based on time synchronization of heterogeneous network between devices that support in IEEE 1588 Standard application framework. With synchronization messages per second, the system was able to accurately synchronize across a single heavily loaded switch. we describes a method of synchronization that provides much more accurate synchronization in systems with larger networks. In this paper, using the IEEE 1588 PTP support for object-oriented modeling techniques through the 'application framework development Development(AFDM)' is proposed. The method described attempts to detect minimum delays, or precision packet probe and packet metrics. The method also takes advantage of the Tablet PC(Primary to Secondary) clock control mechanism to separately control clock rate and time corrections, minimizing overshoot or wild swings in the accuracy of the clock. We verifying the performance of PTP Systems through experiments that proposed method.

• Journal of Institute of Control, Robotics and Systems
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• v.7 no.6
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• pp.550-557
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• 2001

There are several applications and error analysis methods using GPS(Global Positioning System) In most analysis positioning and timing errors are represented as the multiplication of DOP(Dilution Of Precision) and measurement errors, which are affected by the receiver and measurement type. Therefore, lots of DOPs are defined and used to analyze and predict the performance of positioning and timing systems. In this paper, the relationships between these DOPs are investigated in detail, The relationships between GDOP(Geometric DOP), PDOP(Position DOP) and TDOP(Time DOP) in the absolute positioning are de-rived. Using these relationships, the affect of clock bias is analyzed. The relationships between RGDOP(Relative DOP) and PDOP are also derived in relative positioning where the single difference and double dif-ference techniques are used. From the results, it is expected that using the common clock will give better performance when the single difference technique is used while the effects of clock is eliminate when the double difference technique is used. Finally, the error analyses of dual frequency receivers show that the narrow lane measurements give more accurate results than wide line of or L1. L2 independent measurements.

• Journal of Institute of Control, Robotics and Systems
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• v.22 no.8
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• pp.671-677
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• 2016

A Controller Area Network (CAN) is a serial communication protocol that is highly reliable and efficient in many aspects, such as wiring cost and space, system flexibility, and network maintenance. Therefore, it is chosen for the communication protocol between a single chip controller based on Field Programmable Gate Array (FPGA) and peripheral devices. In this paper, the design and implementation of CAN IP, which is written in VHSIC Hardware Description Language (VHDL), is presented. The implemented CAN IP is based on the CAN 2.0A specification. The CAN IP consists of three processes: clock generator, bit timing, and bit streaming. The clock generator process generates a time quantum clock. The bit timing process does synchronization, receives bits from the Rx port, and transmits bits to the Tx port. The bit streaming process generates a bit stream, which is made from a message received from a micro controller subsystem, receives a bit stream from the bit timing process, and handles errors depending on the state of the CAN node and CAN message fields. The implemented CAN IP is synthesized and downloaded into SmartFusion FPGA. Simulations using ModelSim and chip test results show that the implemented CAN IP conforms to the CAN 2.0A specification.

• Journal of Power Electronics
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• v.11 no.3
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• pp.271-278
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• 2011

This paper presents a LLC resonant controller IC for secondary side control without external active devices to achieve low profile and low cost LED back light units. A gate driving transformer is adopted to isolate the primary side and the secondary side instead of an opto-coupler. A new integrated dimming circuitry is proposed to improve the dynamic current control characteristic and the current density of a LED for the brightness modulation of a large screen LCD. A dual-slope clock generator is proposed to overcome the frequency error due to the under shoot in conventional approaches. This chip is fabricated using 0.35 ${\mu}m$ BCD technology and the die size is $2{\times}2\;mm^2$. The frequency range of the clock generator is from 50 kHz to 500 kHz and the range of the dead time is from 50 ns to 2.2 ${\mu}s$. The efficiency of the LED driving circuit is 97 % and the current consumption is 40 mA for a 100 kHz operation frequency from a 15 V supply voltage.

• Korean Journal of Schizophrenia Research
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• v.23 no.1
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• pp.15-28
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• 2020

Objectives: This study investigated the relationship between clock-drawing test (CDT) performance and neuropsychological functions in patients with chronic schizophrenia. Methods: Thirty-one patients with schizophrenia and 30 healthy controls participated in this study. The CDT was administered in three conditions and analyzed using both quantitative and qualitative scoring systems. Comprehensive neuropsychological tests were administered. Results: The results of the quantitative analysis showed that the schizophrenia group performed significantly worse in all three conditions of the CDT compared with the control group. However, no significant differences were observed between the two groups, when the IQ and educational level were controlled. The qualitative analysis showed that the schizophrenia group exhibited significantly more errors in "graphic difficulty" compared with the control group. In addition, CDT quantitative scores were significantly correlated with visuospatial function, memory, attention and executive functions in patients with schizophrenia. Conversely, each qualitative error type was correlated with specific cognitive domains. Furthermore, "graphic difficulty" and "spatial/planning deficit" were identified as predictors of depression symptoms in patients with schizophrenia. Conclusion: The present study demonstrated that the CDT is useful for assessing cognitive dysfunctions in patients with schizophrenia, while qualitative analyses provide more specific information about cognitive deficits compared with quantitative analyses.