• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.5
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• pp.43-50
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• 2004

The clock skew is one of the major constraints for high-speed operation of synchronous integrated circuits. In this paper, we propose a hierarchical partitioning based clock network design algorithm called Advanced Clock Tree Generation (ACTG). Especially new effective partitioning and refinement techniques have been developed in which the capacitance and edge length to each sink are considered from the early stage of clock design. Hierarchical structures obtained by parhtioning and refinement are utilized for balanced clock routing. We use zero skew routing in which Elmore delay model is used to estimate the delay. An overlap avoidance routing algorithm for clock tree generation is proposed. Experimental results show significant improvement over conventional methods.

• Proceedings of the KIEE Conference
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• 2004.11c
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• pp.391-393
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• 2004

For performance and stability of a synchronized system, we need an efficient Clock Tree Synthesis(CTS) methodology to design clock distribution networks. In a system-on-a-chip(SOC) design environment, CTS effectively distributes clock signals from clock sources to synchronized points on layout design. In this paper, we suggest the pre-layout analysis of the clock network including gated clock, multiple clock, and test mode CTS optimization. This analysis can help to avoid design failure with potential CTS problems from logic designers and supply layout constraints so as to get an optimal clock distribution network. Our new design flow including pre-layout CTS analysis and structural violation checking also contributes to reduce design time significantly.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.10
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• pp.1537-1544
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• 2022

When designing chip, it considers design specification, timing problem, and clock synchronization on place & route (P&R) process. P&R process is complicated because of considering various factors. Chip uses clock tree synthesis (CTS) to reduce clock path delay. The purpose of this study is to examine shallow-CTS algorithm for checking clock tree synthesizable. Using open source Parser-Verilog, register transfer level (RTL) synthesizable Verilog file is parsed and it uses Pre-CTS and Post-CTS process that is included shallow-CTS. Based on longest clock path in the Pre-CTS and Post-CTS stages, the standard deviation before and after buffer insertion is compared and analyzed for the accuracy of CTS. In this paper, It is expected that the cost and time problem could be reduced by providing a pre-clock tree synthesis verification method at the RTL level without confirming the CTS result using the time-consuming licensed EDA tool.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.943-946
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• 1999

In this paper, we present a new clock routing algorithm which minimizes total wirelength under any given path-length skew bound. The algorithm onstructs a bounded-skew tree(BST) in two steps:(ⅰ) a bottom-up phase to construct a binary tree of shortest-distance feasible regions which represent the loci of possible placements of clock entry points, and (ⅱ) a top-down phase to determine the exact locations of clock entry points. Experimental results show that our clock routing algorithm, named BST/DME, can produce a set of solutions with skew and wirelength trade-off.

• Journal of information and communication convergence engineering
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• v.6 no.4
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• pp.383-390
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• 2008

Clock skew modeling is important in the performance evaluation and prediction of clock distribution network and it is one of the major constraints for high-speed operation of synchronous integrated circuits. In clock routing synthesis, it is necessary to reduce the clock skew under the specified skew bound, while minimizing the cost such as total wire length and delay. In this paper, a new efficient bounded clock skew routing method is described, which generalizes the well-known bounded skew tree method by allowing loops, i.e., link-edges can be inserted to a clock tree when they are beneficial to reduce the clock skew and/or the wire length. Furthermore, routing topology construction and wire sizing is used to reduce clock delay.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.4
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• pp.643-653
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• 2012

In this paper, we consider a clock tree synthesis technique (CTS) based on buffer insertion method in the multiple clock domain. We propose some detail techniques about the preparing items and the practical method for implementing CTS. We also propose a post processing after CTS implementation. Until now, the buffer insertion-based CTS technique has been widely used, and this paper discusses especially it's practical technique to be applied in the commercial fields to develop ASIC and SoC. CTS is very dependent on the used tool. We use Astro of Synopsys and propose the empirical and theoretical information of the detail techniques for implementing CTS using this tool. We expect that the proposed technique becomes to be good guidelines to backend designers.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.2
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• pp.139-149
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• 2012

A 3D stacked IC is made by multiple dies (possibly) with heterogeneous process technologies. Therefore, die-to-die variation in 2D chips renders on-package variation (OPV) in a 3D chip. In spite of the different variation effect in 3D chips, generally, 3D die stacking can produce high yield due to the smaller individual die area and the averaging effect of variation on data path. However, 3D clock network can experience unintended huge clock skew due to the different clock propagation routes on multiple stacked dies. In this paper, we analyze the on-package variation effect on 3D clock networks and show the necessity of a post silicon management method such as body biasing technique for the OPV induced 3D clock skew control in 3D stacked IC designs. Then, we present a parametric yield improvement method to mitigate the OPV induced 3D clock skew.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.7
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• pp.30-36
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• 2010

Due to the scaling of process parameters, the density on chips has been increasing. This trend increases not only the temperature on chips but also the gradient of the temperature depending on distances. In this paper, we propose the balanced skew tree generation technique for minimizing the clock skew that is affected by the temperature gradients on chips. We calculate the interconnect delay using Elmore delay equation, and find out the optimal balanced clock tree by modifying the clock trees that are generated through the DME(Deferred Merge Embedding) algorithm. We have implemented the proposed technique using C language for the performance evaluation. The experimental results show that the clock insertion point generated by the temperature gradient can be lowered below 54% and we confirm that the skew is remarkably decreased after applying the proposed technique.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1009-1012
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• 1998

An efficient algorithm for clock skew optimization is proposed in this paper. It construct a new clock routing topology which is the generalized graph model while previous methods uses tree-structured routing topology. Edge-insertion technique is used in order to reduce the clock skew. A link-edge is inserted repeatedly between two sinks whose delay difference is large and the distance is small. As a result, the delay of a sink which has the longer delay is decreased and the clock skew is reduced. The proposed algorithm is implemented in C programming language. From the experimental results, we can get the total wire length minimization under the given skew bound.

• The Mathematical Education
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• v.60 no.3
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• pp.249-264
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• 2021

This article is devoted to investigating young learners' understanding of elapsed time from socio-cultural perspectives. The socio-cultural perspective benefits to access and personalize mathematics learning as how to have a mathematical object to be able to realize signifiers with the help of many other mathematical words and mediators. In terms of the realization of signifiers, I analyzed performances on elapsed time tasks of students in Grades 3 (n=115) and interviewed focal students. Quantitative analysis on students' performance identified that students perform differently when the task provided with the analog clock signifier. It suggested that students might think in a different way upon the given signifier even for the same elapsed time, especially when given as the analog clock. Qualitative analysis on focal students' interviews visualized how the students' understanding were different by displaying individual realization trees on elapsed time. The particular location of the analog clock signifier on each realization tree provided a personalized explanation about low performance on the task with analog clock signifier. The finding suggested that the realization of a specific signifier could be a key point in elapsed time understanding. I discussed why a majority of students face difficulty in elapsed time learning indicated analog clock and the advantage of moving elapsed time strands to higher grades in the school mathematics curriculum.