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http://dx.doi.org/10.6109/jkiice.2022.26.10.1537

Lightweighted CTS Preconstruction Techniques for Checking Clock Tree Synthesizable Paths in RTL Design Time  

Kwon, Nayoung (School of Electronic Engineering, Kyungpook National University)
Park, Daejin (School of Electronic Engineering, Kyungpook National University)
Publication Information
Journal of the Korea Institute of Information and Communication Engineering / v.26, no.10, 2022 , pp. 1537-1544 More about this Journal
Abstract
When designing chip, it considers design specification, timing problem, and clock synchronization on place & route (P&R) process. P&R process is complicated because of considering various factors. Chip uses clock tree synthesis (CTS) to reduce clock path delay. The purpose of this study is to examine shallow-CTS algorithm for checking clock tree synthesizable. Using open source Parser-Verilog, register transfer level (RTL) synthesizable Verilog file is parsed and it uses Pre-CTS and Post-CTS process that is included shallow-CTS. Based on longest clock path in the Pre-CTS and Post-CTS stages, the standard deviation before and after buffer insertion is compared and analyzed for the accuracy of CTS. In this paper, It is expected that the cost and time problem could be reduced by providing a pre-clock tree synthesis verification method at the RTL level without confirming the CTS result using the time-consuming licensed EDA tool.
Keywords
Register transfer level; Clock tree synthesis; Synthesizable; Pre-CTS; Post-CTS;
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