• Journal of Broadcast Engineering
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• v.9 no.1
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• pp.83-90
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• 2004

DVB-MHP recommends that NPT(normal play time) be used as the times of stream events. NPT is the local time within an event(TV program). But we found that commercial transport stream (TS) generators and middlewares for DVB-MHP settop boxes are not ready to support the use of NPT by applications. In particular, TS generators do not create NPT reference descriptors needed to reconstruct NPT at the TV receiver. This situation is undesirable because program providers cannot experiment with the idea of synchronized applications. So we have implemented a TS generator that inserts NPT reference descriptors to TS and MyGetNPT API to approximately reconstruct NPT. STC (system time clock) is needed to reconstruct NPT, but Xlets are not allowed to read it. So, we approximate STC by using PCR (program clock reference) and the Java system tune. In this method, the stream generator extrats PCRs from an existing TS and inserts them into null TS packets in the form of MPEG sections, which can be read by Xlets. Because PCRs are displaced into new positions in TS, their values should be adjusted based on the time intervals between the original positions and the new positions. We implemented a synchronized application by using our TS generator and MyGetNPT API, where the task of stream events are to display graphic images. We found that graphic images are displayed where 240 ㎳ from their intended time, where 240ms is a human tolerance for the synchronization skew between graphic image and video.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.12C
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• pp.255-260
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• 2001

This paper describes the design of the Register Controlled DLL(Delay-Locked Loop) that achieves fast locking and low Power consumption using a new locking algorithm. A fashion for a fast locking speed is that controls the two controller in sequence. The up/down signal due to clock skew between a internal and a external clock in phase detector, first adjusts a large phase difference in coarse controller and then adjusts a small phase difference in fine controller. A way for a low power consumption is that only operates one controller at once. Moreover the proposed DLL shows better jitter performance Because using the lock indicator circuit. The proposed DLL circuit is operated from 50MHz to 200MHz by SPICE simulation. The estimated power dissipation is 15mA at 200MHz in 3.3V operation. The locking time is within 7 cycle at all of operating frequency.

• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.4
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• pp.216-231
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• 2001

Several methods for improving device yields and characteristics have been studied by IC manufacturers, as the options for programming components become diversified through the introduction of novel processes. Especially, the sequential repair steps on wafer level and package level are essentially required in DRAMs to improve the yield. Several repair methods for DRAMs are reviewed in this paper. They include the optical methods (laser-fuse, laser-antifuse) and the electrical methods (electrical-fuse, ONO-antifuse). Theses methods can also be categorized into the wafer-level(on wafer) and the package-level(post-package) repair methods. Although the wafer-level laser-fuse repair method is the most widely used up to now, the package-level antifuse repair method is becoming an essential auxiliary technique for its advantage in terms of cost and design efficiency. The advantages of the package-level antifuse method are discussed in this paper with the measured data of manufactured devices. With devices based on several processes, it was verified that the antifuse repair method can improve the net yield by more than 2%~3%. Finally, as an illustration of the usefulness of the package-level antifuse repair method, the repair method was applied to the replica delay circuit of DLL to get the decrease of clock skew from 55ps to 9ps.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.28 no.2
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• pp.457-469
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• 2018

This study aimed to investigate the fundamental reasons for the presence of multi-homed host and the risks associated with such risky system. Furthermore, multi-homed host detection methods that have been researched and developed so far were compared and analyzed to determine areas for improvement. Based on the results, we propose the model of an improved automatic detection system and we implemented it. The experimental environment was configured to simulate the actual network configuration and endpoints of an organization employing network segmentation. And the functionality and performance of the detection system were finally measured while generating multi-homed hosts by category, after the developed detection system had been installed in the experiment environment. We confirmed that the system work correctly without false-positive, false-negative in the scope of this study. To the best of our knowledge, the presented detection system is the first academic work targeting multi-homed host under agent-based.

• Journal of KIISE:Computer Systems and Theory
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• v.35 no.4
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• pp.150-157
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• 2008

This paper presents a design and implementation of realtime video player that operates on a tiled-display system consisting of multiple PCs to provide a very large and high resolution display. In the proposed system, the master process transmits a compressed video stream to multiple PCs using UDP multicast. All slaves(PC) receive the same video stream, decompress, clip their designated areas from the decompressed video frame, and display it to their displays while being synchronized with each other. A simple synchronization mechanism based on the H/W clock of each slave is proposed to avoid the skew between the tiles of the display, and a flow-control mechanism based on the bit-rate of the video stream and a pre-buffering scheme are proposed to prevent the jitter The proposed system is implemented with Microsoft DirectX filter technology in order to decouple the video/audio codec from the player.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.9
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• pp.19-27
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• 2002

Characteristics of interconnect lines considering underlayer geometries of a silicon substrate and crossing metal lines are experimentally analyzed through elaborately devised patterns. In this work, test patterns for transmission lines having several kinds of underlayer geometries were devised, and the signal characteristics and responses are measured by S-parameter and time domain reflection meter (TDR). The patterns were designed and fabricated with a deep-submicron CMOS DRAM technology having 1 Tungsten and 2 Aluminum metals. From the analysis of measured results on the patterns, it is founded that the effects of underlayter line structures on line parameters (especially line capacitance and resistance) and signal distortions occurred from them cannot be negligible. The results provide useful and insightful understanding in the skew balance of package leads and global signal lines such as high-speed clock and data lines.

• Journal of Korea Society of Industrial Information Systems
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• v.6 no.2
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• pp.38-46
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• 2001

This paper presents a new multiprocessor system and corresponding scheduling algorithm that can be applied for implementation of fine grain DSP algorithms such as digital filters. The newly proposed system uses one or more shared buses as the basic interconnection network between processors, and fixed amount of clock-skew is maintained between instruction execution of processors. This system not only can handle the interprocessor communications very efficiently but also can explicitly incorporate the interprocessor communication delay time into the multiprocessor scheduling model. This paper also presents a new scheduling strategy for implementing digital filters expressed in fully-specified flow graphs on the proposed system. The simulation result shows that well-known digital filters can be implemented on proposed multiprocessor in which the implementation satisfies the iteration period bound.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.1 no.2
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• pp.145-158
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• 1997

Method for synchronizing multimedia data is needed to support continuous transmission of multimedia data through a network in a bounded time and it also required for supporting continuous presentation of multimedia data with the required norminal playout rate in distributed network environments. This paper describes a new synchronization method for supporting delay-sensitive multimedia Presentation without degration of Quality of services of multimedia application. It mainly aims to support both intermedia and intermedia synchronization by absorbing network variations which may cause skew or jitter. In order to remove asynchonization problems, we make use of logical time system, dynamic buffer control method, and adjusting synchronization intervals based on the quality of services of a multimedia. It might be more suitable for working on distribute[1 multimedia systems where the network delay variation is changed from time to time and no global clock is supported. And it also can effectively reduce the amount of buffer requirements needed for transfering multimedia data between source and destination system by adjusting synchronization intervals with acceptable packet delay limits and packet loss rates.

• Journal of IKEEE
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• v.26 no.4
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• pp.659-670
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• 2022

An 830-Mb/s/pin transceiver for a controller supporting ×32 LPDDR2 memory is designed. The transmitter consists of eight unit circuits has an impedance in the range of 34Ω ∽ 240Ω, and its impedance is controlled by an impedance correction circuit. The transmitted DQS signal has a phase shifted by 90° compared to the DQ signals. In the receive operation, the read time calibration is performed by per-pin skew calibration and clock-domain crossing within a byte. The implemented transceiver for the LPDDR2 memory controller is designed by using a 55-nm process using a 1.2V supply voltage and has a maximum signal transmission rate of 830 Mb/s/pin. The area and power consumption of each lane are 0.664 mm² and 22.3 mW, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.6
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• pp.18-24
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• 2012

This paper reports the test results of a 50MHz/s 10 bits DAC developed with $0.18{\mu}m$ CMOS process for the wireless sensor network application. The 10bits DAC, not likely a typical segmented type, has been designed as a current driving type with double step thermometer decoding architecture in which 10bits are divided into 6bits of MSB and 4bits of LSB. MSB 6bits are converted into 3 bits row thermal codes and 3 bits column thermal codes to control high current cells, and LSB 4 bits are also converted into thermal codes to control the lower current cells. The high and the lower current cells use the same cell size while a bias circuit has been designed to make the amount of lower unit current become 1/16 of high unit current. All thermal codes are synchronized with output latches to prevent glitches on the output signals. The test results show that the DAC consumes 4.3mA DC current with 3.3V DC supply for 2.2Vpp output at 50MHz clock. The linearity characteristics of DAC are the maximum SFDR of 62.02dB, maximum DNL of 0.37 LSB, and maximum INL of 0.67 LSB.