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Design and Implement of 50MHz 10 bits DAC based on double step Thermometer Code  

Jung, Jun-Hee (Department of Information on Technology, Handong Global University)
Kim, Young-Sik (Department of Information on Technology, Handong Global University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.49, no.6, 2012 , pp. 18-24 More about this Journal
Abstract
This paper reports the test results of a 50MHz/s 10 bits DAC developed with $0.18{\mu}m$ CMOS process for the wireless sensor network application. The 10bits DAC, not likely a typical segmented type, has been designed as a current driving type with double step thermometer decoding architecture in which 10bits are divided into 6bits of MSB and 4bits of LSB. MSB 6bits are converted into 3 bits row thermal codes and 3 bits column thermal codes to control high current cells, and LSB 4 bits are also converted into thermal codes to control the lower current cells. The high and the lower current cells use the same cell size while a bias circuit has been designed to make the amount of lower unit current become 1/16 of high unit current. All thermal codes are synchronized with output latches to prevent glitches on the output signals. The test results show that the DAC consumes 4.3mA DC current with 3.3V DC supply for 2.2Vpp output at 50MHz clock. The linearity characteristics of DAC are the maximum SFDR of 62.02dB, maximum DNL of 0.37 LSB, and maximum INL of 0.67 LSB.
Keywords
DAC; Current cell; Thermometer-decoder; INL; DNL; SFDR;
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Times Cited By KSCI : 2  (Citation Analysis)
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