• BMB Reports
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• v.49 no.11
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• pp.587-589
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• 2016

The circadian clock system enables organisms to anticipate the rhythmic environmental changes and to manifest behavior and physiology at advantageous times of the day. Transcriptional/translational feedback loop (TTFL) is the basic feature of the eukaryotic circadian clock and is based on the rhythmic association of circadian transcriptional activator and repressor. In Drosophila, repression of dCLOCK/CYCLE (dCLK/CYC) mediated transcription by PERIOD (PER) is critical for inducing circadian rhythms of gene expression. Pacemaker neurons in the brain control specific circadian behaviors upon environmental timing cues such as light and temperature cycle. We show that amino acids 657-707 of dCLK are important for the transcriptional activation and the association with PER both in vitro and in vivo. Flies expressing dCLK lacking AA657-707 in $Clk^{out}$ genetic background, homologous to the mouse Clock allele where exon 19 region is deleted, display pacemaker-neuron-dependent perturbation of the molecular clockwork. The molecular rhythms in light-cycle-sensitive pacemaker neurons such as ventral lateral neurons ($LN_vs$) were significantly disrupted, but those in temperature-cycle-sensitive pacemaker neurons such as dorsal neurons (DNs) were robust. Our results suggest that the dCLK-controlled TTFL diversify in a pacemaker-neuron-dependent manner which may contribute to specific functions such as different sensitivities to entraining cues.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.9 s.339
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• pp.29-34
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• 2005

This paper describes a novel internal clock generator, called duty cycle-corrected analog synchronous mirror delay (DCC-ASMD). The proposed circuit is well suited for dual edge-triggered systems such as double data-rate synchronous DRAM since it can achieve clock synchronization within two clock cycles with accurate duty cycle correction. To evaluate the performance of the proposed circuit, DCC-ASMD was designed using a $0.35\mu$m CMOS process technology. Simulation results show that the proposed circuit generates an internal clock having $50\%$ duty ratio within two clock cycles from the external clock having duty ratio range of $40\;\~\;60$.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.6
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• pp.1133-1138
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• 2007

DLLs(Delay Locked Loops) have widely been used in many systems in order to achieve the clock synchronization. A SMD (Synchronous Mirror Delay) structure is used both for skew reduction and for DCC (Duty Cycle Correction). In this paper, a SMD based DLL with DCC using Reduced Delay Lines is proposed in order to reduce the clock skew and correct the duty cycle. The merged structure allows the forward delay array to be shared between the DLL and the DCC, and yields a 25% saving in the number of the required delay cells. The designed chip was fabricated using a $0.25{\mu}m$ 1-poly, 4-metal CMOS process. Measurement results showed the 3% duty cycle error when the input signal ranges from 80% to 20% and the clock frequency ranges from 400MHz to 600MHz. The locking operation needs 3 clock and duty correction requires only 5 clock cycles as feature with SMD structure.

• Journal of Internet Computing and Services
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• v.5 no.4
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• pp.35-42
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• 2004

In this paper the more accurate models than any other ones so far have been proposed for the performance evaluation of single-buffered banyan-type Multistage Interconnection Networks(MINs)'s under nonuniform traffic condition is obtained. Small clock cycle instead of big clock cycle is used. The accuracy of proposed models are conformed by comparing with the results from simulation.

• Journal of Internet Computing and Services
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• v.5 no.5
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• pp.61-68
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• 2004

In this paper, a more accurate model than any other ones so far have been proposed for the performance evaluation of muntibuffered banyan-type Multistage Interconnection Networks(MINs)'s under nonuniform traffic condition is obtained. Small clock cycle instead of big clock cycle is used to improve the performance. The accuracy of the proposed model is conformed by comparing with the results from simulation.

• Journal of Life Science
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• v.27 no.10
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• pp.1225-1231
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• 2017

Disruptive expression patterns of the circadian clock genes are highly associated with many human diseases, including cancer. Cell cycle and proliferation is linked to a circadian rhythm; therefore, abnormal clock gene expression could result in tumorigenesis and malignant development. The molecular network of the circadian clock is based on transcriptional and translational feedback loops orchestrated by a variety of clock activators and clock repressors. The expression of 10~15% of the genome is controlled by the overall balance of circadian oscillation. Among the many clock genes, Period 1 (Per1) and Period 2 (Per2) are clock repressor genes that play an important role in the regulation of normal physiological rhythms. It has been reported that PER1 and PER2 are involved in the expression of cell cycle regulators including cyclins, cyclin-dependent kinases (CDKs), and CDK inhibitors. In addition, correlation of the down-regulation of PER1 and PER2 with development of many cancer types has been revealed. In this review, we focused on the molecular function of PER1 and PER2 in the circadian clock network and the transcriptional and translational targets of PER1 and PER2 involved in cell cycle and tumorigenesis. Moreover, we provide information suggesting that PER1 and PER2 could be promising therapeutic targets for cancer therapies and serve as potential prognostic markers for certain types of human cancers.

• Journal of Integrative Natural Science
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• v.5 no.3
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• pp.198-210
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• 2012

Circadian rhythms govern a remarkable variety of metabolic and physiological functions. Accumulating epidemiological and genetic evidence indicates that the disruption of circadian rhythms might be directly linked to cancer. Intriguingly, several molecular gears constituting the clock machinery have been found to establish functional interplays with regulators of the cell cycle, and alterations in clock function could lead to aberrant cellular proliferation. In addition, connections between the circadian clock and cellular metabolism have been identified that are regulated by chromatin remodelling. This suggests that abnormal metabolism in cancer could also be a consequence of a disrupted circadian clock. Therefore, a comprehensive understanding of the molecular links that connect the circadian clock to the cell cycle and metabolism could provide therapeutic benefit against certain human neoplasias.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.2
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• pp.152-156
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• 2013

This paper presents a fast-lock dual-loop successive approximation register-controlled duty-cycle corrector (SARDCC) circuit using a mixed (binary+sequential) search algorithm. A wider duty-cycle correction range, higher operating frequency, and higher duty-cycle correction accuracy have been achieved by utilizing the dual-loop architecture and the binary search SAR that achieves the fast duty-cycle correcting property. By transforming the binary search SAR into a sequential search counter after the first DCC lock-in, the proposed dual-loop SARDCC keeps the closed-loop characteristic and tracks variations in process, voltage, and temperature (PVT). The measured duty cycle error is less than ${\pm}0.86%$ for a wide input duty-cycle range of 15-85 % over a wide frequency range of 0.5-2.0 GHz. The proposed dual-loop SARDCC is fabricated in a 0.18-${\mu}m$, 1.8-V CMOS process and occupies an active area of $0.075mm^2$.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.8
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• pp.1765-1773
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• 1997

The communication systems which include PLL may have cycle clip problem because of channel noise. The cycle slip problem occurs the synchronization loss of communication system and it may be fatal to the synchronous stream cipher system. While continuous resynchronization is used to lessen the risk of synchronization it has some problems. In this paper, we propose the method which solve the problems by using continuous resynchronization with the clock recovery technique. If the counted value of real clock pulse in reference duration is not same as that of normal state, we decide the cycle slip has occurred. The damaged clock by cycle slip is compensated by adding or subtracting the clock pulse according to the type of cycle slip. It reduced the time for resynchronization by twenty times. It means that 17.8% of data for transmit is compressed.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.28A no.11
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• pp.915-922
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• 1991

This research paper presents an ALU unit using 1.0$\mu$m CMOS technology capable of doing IEEE standard single and double precision floating poing calculation within 32ns (2 clock) at 60 MHz clock speed. This 32ns speed was achieved by using 9ns 1's complement arithmetic 54 bit carry select adder instead of previous 2's complement adders. On the first cycle, this adder is used for addition or subtraction and the second cycle uses this adder for rounding. This reduces the number of required adders from two to one. Speed improvement is 2 to 5 times compared with previous 40MHz design. Design goal was 60MHz, however, this unit is functioning at 80 MHz at room temperature.