• The KIPS Transactions:PartA
• /
• v.17A no.3
• /
• pp.121-126
• /
• 2010

This paper proposes a low-power MOS current-mode logic circuit with the low voltage swing technology and the high-threshold sleep-transistor. The sleep-transistor is used to high-threshold voltage PMOS transistor to minimize the leakage current. The $16{\times}16$ bit parallel multiplier is designed by the proposed circuit structure. Comparing with the conventional MOS current-model logic circuit, the circuit achieves the reduction of the power consumption in sleep mode by 1/104. The proposed circuit is achieved to reduce the power consumption by 11.7% and the power-delay-product by 15.1% compared with the conventional MOS current-model logic circuit in the normal mode. This circuit is designed with Samsung $0.18\;{\mu}m$ standard CMOS process. The validity and effectiveness are verified through the HSPICE simulation.

• Journal of Satellite, Information and Communications
• /
• v.8 no.3
• /
• pp.10-14
• /
• 2013

In this paper, when applying current-mode circuit design technique showing constant power dissipation none the less operation frequency, to the low power design of dynamic voltage frequency scaling, we introduce the low power current-mode circuit design technique applying MOSFET in sub-threshold region, in order to solve the problem that has large power dissipation especially on the condition of low operating frequency. BSIM 3, was used as a MOSFET model in circuit simulation. From the simulation result, the power dissipation of the current memory circuit with sub-threshold MOSFET showed $18.98{\mu}W$, which means the consumption reduction effect of 98%, compared with $900{\mu}W$ in that with strong inversion. It is confirmed that the proposed circuit design technique will be available in DVFS using a current-mode circuit design.

• Transactions on Electrical and Electronic Materials
• /
• v.14 no.5
• /
• pp.235-241
• /
• 2013

A low power CMOS control circuit is applied in an integrated DC-DC buck converter. The integrated converter is composed of a feedback control circuit and power block with 0.35 ${\mu}m$ CMOS process. A current-sensing circuit is integrated with the sense-FET method in the control circuit. In the current-sensing circuit, a current-mirror is used for a voltage follower in order to reduce power consumption with a smaller chip-size. The N-channel MOS acts as a switching device in the current-sensing circuit where the sensing FET is in parallel with the power MOSFET. The amplifier and comparator are designed to obtain a high gain and a fast transient time. The converter offers well-controlled output and accurately sensed inductor current. Simulation work shows that the current-sensing circuit is operated with an accuracy of higher than 90% and the transient time of the error amplifier is controlled within $75{\mu}sec$. The sensing current is in the range of a few hundred ${\mu}A$ at a frequency of 0.6~2 MHz and an input voltage of 3~5 V. The output voltage is obtained as expected with the ripple ratio within 1%.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.23 no.5
• /
• pp.299-304
• /
• 2018

An ideal circuit breaker should supply electric power to loads without losses in a conduction state and completely isolate the load from the power source by providing insulation strength in a break state. Fault current is relatively easy to break in an Alternating Current (AC) circuit breaker because the AC current becomes zero at every half cycle. However, fault current in DC circuit breaker (DCCB) should be reduced by generating a high arc voltage at the breaker contact point. Large fire may occur if the DCCB does not take sufficient arc voltage and allows the continuous flow of the arc fault current with high temperature. A semiconductor circuit breaker with a power electronic device has many advantages. These advantages include quick breaking time, lack of arc generation, and lower noise than mechanical circuit breakers. However, a large load capacity cannot be applied because of large conduction loss. An extinguishing technology of DCCB with polymeric positive temperature coefficient (PPTC) device is proposed and evaluated through experiments in this study to take advantage of low conduction loss of mechanical circuit breaker and arcless breaking characteristic of semiconductor devices.

• ETRI Journal
• /
• v.19 no.2
• /
• pp.35-47
• /
• 1997

A power amplifier operating at 3.3 V has been developed for CDMA/AMPS dual-mode cellular phones. It consists of linear GaAs power MESFET's, a new gate bias control circuit, and an output matching circuit which prevents the drain terminal of the second MESF from generating the harmonics. The relationship between the intermodulation distortion and the spectral regrowth of the power amplifier has been investigated with gate bias by using the two-tone test method and the adjacent channel leakage power ratio (ACPR) method of CDMA signals. The dissipation power of the power amplifier with a gate bias control circuit is minimized to below 1000 mW in the range of the low power levels while satisfying the ACPR of less than -26 dBc for CDMA mode. The ACPR of the power amplifier is measured to be -33 dBc at a high output power of 26 dBm.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.25 no.2
• /
• pp.87-93
• /
• 2020

This study proposes a gate driver that operates semiconductor switches in the bipolar pulsed power modulator. The proposed gate driver was designed to receive isolated power and synchronized signals through the gate transformer. The gate circuit has a separate delay in the on-and-off operation to prevent a short circuit between the top and bottom switches of each leg. On the basis of the proposed gate circuit, a bipolar pulsed power modulator prototype with a 2.5 kV/100 A rating was developed. Finally, the bipolar pulsed power modulator was tested under resistive load and plasma reactor load conditions. It is verified that the proposed gate driver can be applied to a bipolar pulsed power modulator.

• Proceedings of the IEEK Conference
• /
• 1998.10a
• /
• pp.703-706
• /
• 1998

This paper presents an efficient substrate-bias generator(SBG)for low-power, high-density DRAM's The proposed SBG can supply stable voltage with switching the supply voltage of driving circuit, and it can substitude the small capacitance for the large capacitance. The charge pumping circuit of the SBG suffere no VT loss and is to be applicable to low-voltage DRAM's. Also it can reduce the power consumption to make VBB because of it's high pumping efficiency. Using biasing voltage with positive temperature coefficient, VBB level detecting circuit can detect constant value of VBB against temperature variation. VBB level during VBB maintaining period varies 0.19% and the power dissipation during this period is 0.16mw. Charge pumping circuit can make VBB level up to -1.47V using VCC-1.5V, and do charge pumping operation one and half faster than the conventional ones. The temperature dependency of the VBB level detecting circuit is 0.34%. Therefore the proposed SBG is expected to supply a stable VBB with less power consumption when it is used in low power DRAM's.

• Proceedings of the KIEE Conference
• /
• 2000.07e
• /
• pp.85-88
• /
• 2000

This paper was development a discharge lamp ballast in order to wave improvement of high power factor and high efficiency. The discharge lamp ballast consists of a power factor correction circuit and a correction circuit on switching frequency of inverter. Instead of passive power factor circuit, active power factor circuit is adopted. Because it has the advantage of size, weight, total harmonic distortion, out DC voltage regulation, and power factor. The power factor circuit with MG34262 is controlled by variable frequency discontinuous mode. Results experiments, discharge lamp ballast is showed to have excellent for the proposed electronic ballast's operation and characteristics.

• Journal of Power Electronics
• /
• v.11 no.5
• /
• pp.669-676
• /
• 2011

A novel polarity inversion dc-dc power conversion circuit that features the high input to output step-up voltage conversion ratio characteristics is presented for high voltage DC power supply applications. The proposed circuit features the reduced voltage stresses of the components compared to those of the conventional ones. The operational principles of the proposed circuit are analyzed and comparative features are presented. The simulation results and experimental results are presented to verify the validity of the proposed circuit.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.28 no.1
• /
• pp.76-81
• /
• 2023

A new test circuit for an MMC-based valve HVDC power converter is proposed. The proposed scheme satisfies the required clauses from IEC-62501. The valve test current contains second harmonic component and DC offset as well as a fundamental component that is quite similar to the real operating arm current of MMC based HVDC power system. The structure of the proposed test circuit is simple compared to conventional test circuits. Furthermore, the power supply voltage rating of the proposed test circuit is reduced dramatically around 20% of the conventional scheme with the same current rating. The validity of the proposed test circuit is verified through simulation and experimental results.