• 한국전기전자재료학회논문지
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• 제18권6호
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• pp.560-570
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• 2005

In this paper, a microelectrode away DNA chip was fabricated on glass slide using photolithography technology. Several probe DNAs consisting of mercaptohexyl moiety at their 5' end were immobilized on the gold electrodes by DNA arrayer utilizing the affinity between gold and sulfu. Then target DNAs were hybridized and reacted with Hoechst 33258, which is a DNA minor groove binder and electrochemically active dye. Cyclic voltammetry in 5mA ferricyanide/ferrocyanide solution at 100 mV/s confirmed the immobilization of probe DNA on the gold electrodes. Linear sweep voltammetry or cyclic voltammetry showed a difference between target DNA and control DNA in the anodic peak current values. It was derived from Hoechst 33258 concentrated at the electrode surface through association with formed hybrid. It suggested that this DNA chip could recognize the sequence specific genes. It suggested that multichannel electrochemical DNA microarray is useful to develop a portable device for clinical gene diagnostic system.

• 한국방송∙미디어공학회:학술대회논문집
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• 한국방송공학회 2003년도 정기총회 및 학술대회
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• pp.69-72
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• 2003

This paper presents a signal processing IC for digital HDTV, which is designed to operate in bunt-in HDW or in HD-set-top Box. The chip supports de-multiplexing an ISO/IEC 13818-1 MPEG-2 TS stream. It decodes MPEG-2 MP@HL video bitstream, and provides high-quality scaled video for display on HDTV monitor. The chip consists of ARM7TDMI for TS-Demux, PCI interface, Audio interface, MPEG2 MP@HL video decoder Display processor, Graphic processor, Memory controller, Audio int3face, Smart Card interface and UART. It is fabricated using Sam sung's 0.18-um and the package of 492-pin BGA is used.

• 청정기술
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• 제27권3호
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• pp.240-246
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• 2021

COF (Chip on film)용 폐에칭용액 내 구리가 약 3.5% 함유되어 있으며, 철 시편을 사용한 시멘테이션을 통해 구리를 회수하고자 하였다. 철 시편 3종류(플레이트, 칩, 분말)에 따른 시멘테이션 반응에 미치는 영향을 조사하였으며, 구리의 회수율을 높이고자 구리에 대한 철의 몰 비를 변수로 하였다. 반응 전·후 용액 내 시간에 따른 구리 농도의 변화를 확인하였으며, 몰 비를 증가시킬수록 초기 용액 내 구리 함량이 급격히 줄어드는 경향이 나타났다. 상온에서 1시간의 시멘테이션 반응 후 철 시편의 비표면적 값이 큰 플레이트, 칩, 분말 순으로 구리의 회수율이 증가하였다. 회수된 분말은 X선 회절 분석기(X-ray diffraction, XRD), 주사전자현미경(scanning electron microscopy, SEM) 및 에너지 분산형 분광분석법(Energy-dispersive X-ray spectroscopy, EDM) 분석을 통해 결정상과 결정 형태를 확인하였으며, 철 분말의 경우에는 회수된 구리 분말에 미반응된 철 성분이 혼재하였다. 구리에 대한 철의 몰 비 4의 조건으로 철 칩을 사용하였을 때, 구리 회수율 약 98.4%로 최적 조건으로 달성하였다.

• 마이크로전자및패키징학회지
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• 제7권4호
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• pp.17-22
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• 2000

In this paper, methods to analyze wire sweep during the semiconductor chip encapsulation have been studied. The wire sweep analysis is used to analyze the deformation of bonding wires that connect the chip to the leadframe during encapsulation. The analysis is done using either analytical solutions or numerical simulation. The analytical solution is used for rough but fast calculation of wire sweep. The results from the numerical simulation are closest to the experimental results.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2002년도 International Meeting on Information Display
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• pp.963-968
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• 2002

This paper will review the driving methods and issues of driving circuitry for passive matrix organic electro-luminescent displays(PM-OELDs). And it will shows the proposed one-chip and two-chip solution for driving the PM-OELDs and also the pixel structure and driving methods of active matrix (AM-OELDs). We will discuss the proper applications of OELDs with its power consumption by comparison with that of LCD.

• 정보화사회
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• 통권129호
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• pp.42-49
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• 1999

디지털 비디오의 혁명이 가시화 되면서 가정의 각 Consumer기기들 간의 고속 Digital Interface가 요구되어져 왔다. 이러한 요구의 예는 MPEG-2 Transport Stream을 이용한 Set-Top Bx, Digital Television, DVCR 또는 Camcorder간의 Interface와 Interactive Games, Computers 및 주변기기간의 Control/Data Interface를 포함하고 있다. 엄밀히 말해 Data의 일반적인 전송을 지원하는 Interface가 요구되어지며, IEEE1394 Standard는 이에 대한 최적의 Solution을 제공해 준다. 본 기술은 IEEE1394를 기반으로 MPEG-2 Transport Stream을 주고받을 수 있는 방법을 제공하기 위한 Hardware를 개발하는 기술인 MPEG2용 IEEE1394 Link Chip Set 개발 기술에 대하여 설명한다.

• ETRI Journal
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• 제38권6호
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• pp.1240-1249
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• 2016

With the number of IP cores in a multicore system-on-chip increasing to up to tens or hundreds, the role of on-chip interconnection networks is vital. We propose a networks-on-chip-style bus network as a compromise and redefine the exploration problem to find the best IP tiling patterns and communication path combinations. Before solving the problem, we estimate the time complexity and validate the infeasibility of the solution. To reduce the time complexity, we propose two fast exploration algorithms and develop a program to implement these algorithms. The program is executed for several experiments, and the exploration time is reduced to approximately 1/22 and 7/1,200 at the first and second steps of the exploration process, respectively. However, as a trade-off for the time saving, the time cost (TC) of the searched architecture is increased to up to 4.7% and 11.2%, respectively, at each step compared with that of the architecture obtained through full-case exploration. The reduction ratio can be decreased to 1/4,000 by simultaneously applying both the algorithms even though the resulting TC is increased to up to 13.1% when compared with that obtained through full-case exploration.

• ETRI Journal
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• 제40권6호
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• pp.759-773
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• 2018

Uncore components such as on-chip memory systems and on-chip interconnects consume a large amount of energy in emerging embedded applications. Few studies have focused on next-generation analytical models for future chip-multiprocessors (CMPs) that simultaneously consider the impacts of the power consumption of core and uncore components. In this paper, we propose a convex-optimization approach to design heterogeneous uncore architectures for embedded CMPs. Our convex approach optimizes the number and placement of memory banks with different technologies on the memory layer. In parallel with hybrid memory architecting, optimizing the number and placement of through silicon vias as a viable solution in building three-dimensional (3D) CMPs is another important target of the proposed approach. Experimental results show that the proposed method outperforms 3D CMP designs with hybrid and traditional memory architectures in terms of both energy delay products (EDPs) and performance parameters. The proposed method improves the EDPs by an average of about 43% compared with SRAM design. In addition, it improves the throughput by about 7% compared with dynamic RAM (DRAM) design.

• 한국주조공학회지
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• 제38권2호
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• pp.32-40
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• 2018

Changes in the microstructures and mechanical properties of an AC2B alloy through solution heat treatment were investigated using recycled AC2B cutting chips as raw material. The as-cast microstructure of the AC2B alloy comprised ${\alpha}$-Al, $Al_2Cu$, and coarse needle-shaped phases considered to be eutectic Si and an Al-Fe-Si based intermetallic compound. After solution heat treatments at $505^{\circ}C$ for 1 h and 6 h, the samples showed complete dissolution of $Al_2Cu$ and relatively fine distribution of intermetallic compounds. Hardness test results showed that the hardness rapidly increased after the solution heat treatment for 1 h by solid solution hardening, and the increase of hardness exhibited a plateau from 1 h to 6 h. The results of the hardness and tensile tests showed that there was no visible difference in the effect of 1 h and 6 h solid solution treatment.

• 한국재료학회:학술대회논문집
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• 한국재료학회 1998년도 IUMRS-ICEM ABSTRACT BOOK
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• pp.139.4-139
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• 1998