• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.11
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• pp.1707-1712
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• 2013

In this paper, we implement a hardware for motor control based on FPGA + embedded processor using Zynq EPP which is All Programmable SoC in order to improve a structural problem of motion control based on such as DSP, MCU and FPGA previously. The implemented motor controller that is fused controller with advantage of FPGA and embedded processor. The signal processing part of high velocity motor control is performed by motor controller based on FPGA. A motion profile and kinematic calculation that are required algorithm process such as operation of a complicate decimal point has processed in an embedded processor based on dual core. As a result of a hardware implementation, it has an advantage that has can be realized an effect of distribution process in one chip. It has also an advantage that is able to organize as a multi-axis motor controller through adding the IP core of motor control implemented on FPGA.

• Smart Structures and Systems
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• v.6 no.5_6
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• pp.579-593
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• 2010

Low-power radio frequency (RF) chip transceiver technology and the associated structural health monitoring platforms have matured recently to enable high-rate, lossless transmission of measurement data across large-scale sensor networks. The intrinsic value of these advanced capabilities is the allowance for high-quality, rapid operational modal analysis of in-service structures using distributed accelerometers to experimentally characterize the dynamic response. From the analysis afforded through these dynamic data sets, structural identification techniques can then be utilized to develop a well calibrated finite element (FE) model of the structure for baseline development, extended analytical structural evaluation, and load response assessment. This paper presents a case study in which operational modal analysis is performed on a three-span prestressed reinforced concrete bridge using a wireless sensor network. The low-power wireless platform deployed supported a high-rate, lossless transmission protocol enabling real-time remote acquisition of the vibration response as recorded by twenty-nine accelerometers at a 256 Sps sampling rate. Several instrumentation layouts were utilized to assess the global multi-span response using a stationary sensor array as well as the spatially refined response of a single span using roving sensors and reference-based techniques. Subsequent structural identification using FE modeling and iterative updating through comparison with the experimental analysis is then documented to demonstrate the inherent value in dynamic response measurement across structural systems using high-rate wireless sensor networks.

• Korean Journal of Veterinary Service
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• v.44 no.4
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• pp.185-194
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• 2021

Polyglutamine extension in the coding sequence of mutant huntingtin causes neuronal degeneration associated with the formation of insoluble polyglutamine aggregates in Huntington's disease (HD). Mutant huntingtin can form aggregates within the nucleus and processes of neurons possibly due to misfolding of the proteins. To better understand the mechanism by which an elongated polyglutamine causes aggregates, we have developed an in vitro binding assay system of polyglutamine tract from truncated huntingtin. We made GST-HD exon1 fusion proteins which have expanded polyglutamine epitopes (e.g., 17, 23, 32, 46, 60, 78, 81, and 94 CAG repeats). In the present emergence of new study adjusted nanotechnology on protein chip such as surface plasmon resonance strategy which used to determine the substance which protein binds in drug discovery platform is worth to understand better neurodegenerative diseases (i.e., Alzheimer disease, Parkinson disease and Huntington disease) and its pathogenesis along with development of therapeutic measures. Hence, we used strengths of surface plasmon resonance (SPR) technology which is enabled to examine binding specificity and explore targeted molecular epitope using its electron charged wave pattern in HD pathogenesis utilize conjugated mutant epitope of HD protein and its interaction whether wild type GST-HD interacts with mutant GST-HD with maximum binding affinity at pH 6.85. We found that the maximum binding affinity of GST-HD17 with GST-HD81 was higher than the binding affinities of GST-HD17 with other mutant GST-HD constructs. Furthermore, our finding illustrated that the mutant form of GST-HD60 showed a stronger binding to GST-HD23 or GST-HD17 than GST-HD60 or GST-HD81. These results indicate that the binding affinity of mutant huntingtin does not correlate with the length of polyglutamine. It suggests that the aggregation of an expanded polyglutamine might have easily occurred in the presence of wild type form of huntingtin.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.18 no.1
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• pp.21-31
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• 2017

In this paper, the Zynq system-on-chip (SoC) platform is used to design an adaptive noise reduction and edge-detection system using partial reconfiguration. Filters are implemented in a partially reconfigurable (PR) region to provide high computational complexity in real-time, 1080p video processing. In addition, partial reconfiguration enables better utilization of hardware resources in the embedded system from autonomous replacement of filters in the same PR region. The proposed edge-detection system performs adaptive noise reduction if the noise density level in the incoming video sequences exceeds a given threshold value. Results of implementation show that the proposed system improves the accuracy of edge-detection results (14~20 times in Pratt's Figure of Merit) through self-reconfiguration of filter bitstreams triggered by noise density level in the video sequences. In addition, the ZyCAP controller implemented in this paper enables about 2.1 times faster reconfiguration when compared to a PCAP controller.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.1 s.343
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• pp.27-36
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• 2006

Conventional delay-insensitive (DI) data encodings usually require 2N+1 wires for transferring N-bit. To reduce complexity and power dissipation of wires in designing a large scaled chip, an encoder and a decoder circuits, where N-bit data transfer can be peformed with only N+l wires, are proposed. These circuits are based on a quasi delay-insensitive (QDI) model and designed by using current-mode multiple valued logic (CMMVL). The effectiveness of the proposed data transfer mechanism is validated by comparisons with conventional data transfer mechanisms using dual-rail and 1-of-4 encodings through simulation at the 0.25 um CMOS technology. In general, simulation results with wire lengths of 4 mm or larger show that the CMMVL scheme significantly reduces delay-power product ($D{\ast}P$) values of the dual-rail encoding with data rate of 5 MHz or more and the 1-of-4 encoding with data rate of 18 MHz or more. In addition, simulation results using the buffer-inserted dual-rail and 1-of-4 encodings for high performance with the wire length of 10 mm and 32-bit data demonstrate that the proposed CMMVL scheme reduces the D*P values of the dual-rail encoding with data rate of 4 MHz or more and 1-of-4 encoding with data rate of 25 MHz or more by up to $57.7\%\;and\;17.9\%,$ respectively.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.5
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• pp.445-453
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• 2016

This paper presents the implementation and design of the 1T-1R wireless HD video streaming systems over 28 GHz mmWave frequency using 3GPP LTE-TDD standard on NI USRP RIO SDR platform. The baseband of the system uses USRP RIO that are stored in Xilinx Kintex-7 chip to implement LTE-TDD transceiver modem, the signal that are transceived from USRP RIO up or down converts to 28 GHz by using self-designed 28 GHz RF transceiver modules and it is finally communicated HD video data through self-designed $4{\times}8$ sub array antennas. It is that communication method between USRP RIO and Host PC use PCI express ${\times}4$ to minimize delay of data to transmit and receive. The implemented system show high error vector magnitude performance above 25.85 dBc and to transceive HD video in experiment environment anywhere.

• KSBB Journal
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• v.22 no.6
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• pp.371-377
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• 2007

Polyhydroxyalkanoates (PHAs) are a family of microbial polyesters that can be produced by fermentation from renewable resources. PHAs can be used as completely biodegradable plastics or elastomers. In this paper, novel applications of PHAs in biosensor are described. A general platform technology was developed by using the substrate binding domain (SBD) of PHA depolymerase as a fusion partner to immobilize proteins of interest on PHA surface. It could be shown that the proteins fused to the SBD of PHA depolymerase could be specifically immobilized onto PHA film, PHA microbead, and microcontact printed PHA surface. We review the results obtained for monitoring the specific interaction between the SBO and PHA by using enhanced green fluorescent protein, red fluorescent protein, single chain antibody against hepatitis B virus preS2 surface protein and severe acute respiratory syndrome coronavirus surface antigen as model proteins. Thus, this system can be efficiently used for studying protein-protein and possibly protein-biomolecule interactions for various biotechnological applications.

• The Journal of the Convergence on Culture Technology
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• v.9 no.6
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• pp.967-971
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• 2023

Recently, a variety of AI-based platform services are available, and one of them is ChatGPT that processes a large quantity of data in the natural language and generates an answer after self-learning. ChatGPT can perform various tasks including software programming in the IT sector. Particularly, it may help generate a simple program and correct errors using C Language, which is a major programming language. Accordingly, it is expected that ChatGPT is capable of effectively using Verilog HDL, which is a hardware language created in C Language. Verilog HDL synthesis, however, is to generate imperative sentences in a logical circuit form and thus it needs to be verified whether the products are executed properly. In this paper, we aim to select small-scale logical circuits for ease of experimentation and to verify the results of circuits generated by ChatGPT and human-designed circuits. As to experimental environments, Xilinx ISE 14.7 was used for module modeling, and the xc3s1000 FPGA chip was used for module embodiment. Comparative analysis was performed on the use area and processing time of FPGA to compare the performance of ChatGPT products and Verilog HDL products.