• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.31 no.5
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• pp.307-312
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• 2018

Liquid phases in ZnO varistors cause more complex phase development and microstructure, which makes the control of electrical properties and reliability more difficult. Therefore, we have investigated 2 mol% $CaCO_3$ doped $ZnO-Co_3O_4-Cr_2O_3-La_2O_3$ (ZCCLCa) bulk ceramics as one of the compositions without liquid phase sintering additive. The results were as follows: when $CaCO_3$ is added to ZCCLCa ($644{\Omega}cm$) acting as a simple ohmic resistor, CaO does not form a secondary phase with ZnO but is mostly distributed in the grain boundary and has excellent varistor characteristics (high nonlinear coefficient ${\alpha}=78$, low leakage current of $0.06{\mu}A/cm^2$, and high insulation resistance of $1{\times}10^{11}{\Omega}cm$). The main defects $Zn_i^{{\cdot}{\cdot}}$ (AS: 0.16 eV, IS & MS: 0.20 eV) and $V_o^{\bullet}$ (AS: 0.29 eV, IS & MS: 0.37 eV) were found, and the grain boundaries had 1.1 eV with electrically single grain boundary. The resistance of each defect and grain boundary decreases exponentially with increasing the measurement temperature. However, the capacitance (0.2 nF) of the grain boundary was ~1/10 lower than that of the two defects (~3.8 nF, ~2.2 nF) and showed a tendency to decrease as the measurement temperature increased. Therefore, ZCCLCa varistors have high sintering temperature of $1,200^{\circ}C$ due to lack of liquid phase additives, but excellent varistor characteristics are exhibited, which means ZCCLCa is a good candidate for realizing chip type or disc type commercial varistor products with excellent performance.

• Analytical Science and Technology
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• v.11 no.2
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• pp.112-119
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• 1998

A Siemens SemiQuant (SSQ) 3000 program, a precalibrated 'standardless' analytical program handling up to 90 elements, was evaluated for the fast analysis of various types of reference materials using a wavelength dispersive X-ray spectrometer. Various types of standard reference materials such as metal discs, metal chips, and geological materials in powder form were analysed and it took 23 minutes of measuring time for 75 elements. Measurements of geological reference materials using different sampling methods were carried out and their data were interactively evaluated. The analysis of materials of a known matrix concentration such as stainless steels provided higher precision value compared to totally unknown samples. The analyses of materials prepared as pressed pellets or fused glass beads provided higher precision values compared to the measurement of loose powders with a foil on the sample surface and helium operation, though their sampling procedures were more complicate and took more time. Since very light elements such as boron, carbon, and oxygen have a strong influence on the matrix effects and also on the calculation of effective matrix corrections, the rhodium Compton check was applied to verify the reliability of the defined light element concentrations of light matrix materials and the defined major sample compounds. Failure of defining correct matrix resulted in an unoptimized matrix correction and therefore in the wrong calculation of the element concentration.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.4
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• pp.913-920
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• 2011

In this paper, a logic process based 1-kbit EEPROM IP for RFID tag chips of 900MHz is designed. The cell array of the designed 1-kbit EEPROM IP is arranged in a form of four blocks of 16 rows x 16 columns, that is in a two-dimensional arrangement of one-word EEPROM phantom cells. We can reduce the IP size by making four memory blocks share CG (control gate) and TG (tunnel gate) driver circuits. We propose a TG switch circuit to supply respective TG bias voltages according to operational modes and to keep voltages between devices within 5.5V in terms of reliability in order to share the TG driver circuit. Also, we can reduce the power consumption in the read mode by using a partial activation method to activate just one of four memory blocks. Furthermore, we can reduce the access time by making BL (bit line) switching times faster in the read mode from reduced number of cells connected to each column. We design and compare two 1-kbit EEPROM IPs, two blocks of 32 rows ${\times}$ 16 columns and four blocks of 16 rows ${\times}$ 16 columns, which use Tower's $0.18{\mu}m$ CMOS process. The four-block IP is smaller by 11.9% in the layout size and by 51% in the power consumption in the read mode than the two-block counterpart.

• Journal of the Microelectronics and Packaging Society
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• v.18 no.4
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• pp.11-18
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• 2011

The quantitative interfacial adhesion energy of the Cu-Cu direct bonding layers was evaluated in terms of the bonding temperature and Ar+$H_2$ plasma treatment on Cu surface by using a 4-point bending test. The interfacial adhesion energy and bonding quality depend on increased bonding temperature and post-annealing temperature. With increasing bonding temperature from $250^{\circ}C$ to $350^{\circ}C$, the interfacial adhesion energy increase from $1.38{\pm}1.06$ $J/m^2$ to $10.36{\pm}1.01$ $J/m^2$. The Ar+$H_2$ plasma treatment on Cu surface drastically increase the interfacial adhesion energy form $1.38{\pm}1.06$ $J/m^2$ to $6.59{\pm}0.03$ $J/m^2$. The plasma pre-treatment successfully reduces processing temperature of Cu to Cu direct bonding.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.239-240
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• 2012

With advancements in semiconductor device technologies, manufacturing processes are getting more complex and it became more difficult to maintain tighter process control. As the number of processing step increased for fabricating complex chip structure, potential fault inducing factors are prevail and their allowable margins are continuously reduced. Therefore, one of the key to success in semiconductor manufacturing is highly accurate and fast fault detection and classification at each stage to reduce any undesired variation and identify the cause of the fault. Sensors in the equipment are used to monitor the state of the process. The idea is that whenever there is a fault in the process, it appears as some variation in the output from any of the sensors monitoring the process. These sensors may refer to information about pressure, RF power or gas flow and etc. in the equipment. By relating the data from these sensors to the process condition, any abnormality in the process can be identified, but it still holds some degree of certainty. Our hypothesis in this research is to capture the features of equipment condition data from healthy process library. We can use the health data as a reference for upcoming processes and this is made possible by mathematically modeling of the acquired data. In this work we demonstrate the use of recurrent neural network (RNN) has been used. RNN is a dynamic neural network that makes the output as a function of previous inputs. In our case we have etch equipment tool set data, consisting of 22 parameters and 9 runs. This data was first synchronized using the Dynamic Time Warping (DTW) algorithm. The synchronized data from the sensors in the form of time series is then provided to RNN which trains and restructures itself according to the input and then predicts a value, one step ahead in time, which depends on the past values of data. Eight runs of process data were used to train the network, while in order to check the performance of the network, one run was used as a test input. Next, a mean squared error based probability generating function was used to assign probability of fault in each parameter by comparing the predicted and actual values of the data. In the future we will make use of the Bayesian Networks to classify the detected faults. Bayesian Networks use directed acyclic graphs that relate different parameters through their conditional dependencies in order to find inference among them. The relationships between parameters from the data will be used to generate the structure of Bayesian Network and then posterior probability of different faults will be calculated using inference algorithms.

• Tuberculosis and Respiratory Diseases
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• v.76 no.2
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• pp.75-79
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• 2014

Trichloroethylene (TCE) is a toxic chemical commonly used as a degreasing agent, and it is usually found in a colorless or blue liquid form. TCE has a sweet, chloroform-like odor, and this volatile chlorinated organic chemical can cause toxic hepatitis, neurophysiological disorders, skin disorders, and hypersensitivity syndromes. However, the hypersensitivity pneumonitis (HP) attributed to TCE has rarely been reported. We hereby describe a case of HP associated with TCE in a 29-year-old man who was employed as a lead welder at a computer repair center. He was installing the capacitors on computer chip boards and had been wiped down with TCE. He was admitted to our hospital with complaints of dry coughs, night sweats, and weight losses for the past two months. HP due to TCE exposure was being suspected due to his occupational history, and the results of a video-associated thoracoscopic biopsy confirmed the suspicions. Symptoms have resolved after the steroid pulse therapy and his occupational change. TCE should be taken into consideration as a potential trigger of HP. Early recognition and avoidance of the TCE exposure in the future is important for the treatment of TCE induced HP.

• Applied Chemistry for Engineering
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• v.32 no.4
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• pp.461-466
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• 2021

In this article, a portable and cost-effective voltammetric biosensor with nanoparticles was developed for the measurements of heterogeneous nuclear ribonucleoprotein A1 protein (hnRNP A1) biomarker which can potentially be used for lung cancer diagnosis. Gold nanoparticles were first electrodeposited onto screen printed carbon electrode (SPCE) followed by immobilizing a single stranded DNA aptamer specific to hnRNP A1 onto the electrode surface. Ethanolamine was also used when immobilizing DNA aptamer on the surface to prevent signals from non-specific adsorption events. Sequential injection of hnRNP A1 biomarker and anti-hnRNP A1 conjugated with alkaline phosphatase (ALP) onto the aptamer chip surface allows to form the sandwich complex of DNA aptamer/hnRNP A1/ALP-anti-hnRNP A1 on the electrode surface which further reacted with 4-aminophenyl phosphate (APP). The electrocatalytic reaction of the enzyme, ALP, and the substrate, APP, resulting in the oxidative current response changes at -0.05 and -0.17 V (vs. Ag/AgCl) against the hnRNP A1 concentration was measured using cyclic and differential pulse voltammetry, respectively. The Au nanoparticles-integrated voltammetric biosensor was applied to analyze human normal serum solutions possibly suggesting potential applicability for lung cancer diagnosis.

• Journal of the Microelectronics and Packaging Society
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• v.28 no.2
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• pp.71-79
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• 2021

In this study, we have successfully fabricated the Sn-Ni paste and evaluated the bonding properties for high-temperature endurable EV (Electric Vehicle) power module applications. From evaluating of the micro-structural changes in the TLPS (Transient Liquid Phase Sintering) joints with Sn and Ni contents in the Sn-Ni pastes, a lack of Ni powders and Ni particle agglomerations by Ni surplus were observed in the Sn-20Ni and Sn-50Ni joints (in wt.%), respectively. In contrast, relatively dense microstructures are observed in the Sn-30Ni and Sn-40Ni TLPS joints. From differential scanning calorimetry (DSC) thermal analysis results of the fabricated Sn-Ni paste and TLPS bonded joints, we confirmed that the complete reactions of Sn with Ni to form Ni-Sn intermetallic compounds (IMCs) at bonding temperatures occurred, and there is no remaining Sn in the joints after TLPS bonding. In addition, the interfacial reactions and IMC phase changes of the Sn-30Ni joints under various bonding temperatures were reported, and their mechanical shear strength were investigated. The TLPS bonded joints were mainly composed of residual Ni particles and Ni₃Sn₄ intermetallic phase. The average shear strength tended to increase with increasing bonding temperature. Our results indicated a high shear strength value of approximately 30 MPa at a bonding temperature of 270 ℃ and a bonding time of 30 min.

• The Journal of the Convergence on Culture Technology
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• v.9 no.6
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• pp.967-971
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• 2023

Recently, a variety of AI-based platform services are available, and one of them is ChatGPT that processes a large quantity of data in the natural language and generates an answer after self-learning. ChatGPT can perform various tasks including software programming in the IT sector. Particularly, it may help generate a simple program and correct errors using C Language, which is a major programming language. Accordingly, it is expected that ChatGPT is capable of effectively using Verilog HDL, which is a hardware language created in C Language. Verilog HDL synthesis, however, is to generate imperative sentences in a logical circuit form and thus it needs to be verified whether the products are executed properly. In this paper, we aim to select small-scale logical circuits for ease of experimentation and to verify the results of circuits generated by ChatGPT and human-designed circuits. As to experimental environments, Xilinx ISE 14.7 was used for module modeling, and the xc3s1000 FPGA chip was used for module embodiment. Comparative analysis was performed on the use area and processing time of FPGA to compare the performance of ChatGPT products and Verilog HDL products.

• Clean Technology
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• v.29 no.4
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• pp.255-261
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• 2023

Power semiconductors are semiconductors used for power conversion, transformation, distribution, and control. Recently, the global demand for high-voltage power semiconductors is increasing across various industrial fields, and optimization research on high-voltage IGBT components is urgently needed in these industries. For high-voltage IGBT development, setting the resistance value of the wafer and optimizing key unit processes are major variables in the electrical characteristics of the finished chip. Furthermore, the securing process and optimization of the technology to support high breakdown voltage is also important. Etching is a process of transferring the pattern of the mask circuit in the photolithography process to the wafer and removing unnecessary parts at the bottom of the photoresist film. Ion implantation is a process of injecting impurities along with thermal diffusion technology into the wafer substrate during the semiconductor manufacturing process. This process helps achieve a certain conductivity. In this study, dry etching and wet etching were controlled during field ring etching, which is an important process for forming a ring structure that supports the 3.3 kV breakdown voltage of IGBT, in order to analyze four conditions and form a stable body junction depth to secure the breakdown voltage. The field ring ion implantation process was optimized based on the TEG design by dividing it into four conditions. The wet etching 1-step method was advantageous in terms of process and work efficiency, and the ring pattern ion implantation conditions showed a doping concentration of 9.0E13 and an energy of 120 keV. The p-ion implantation conditions were optimized at a doping concentration of 6.5E13 and an energy of 80 keV, and the p+ ion implantation conditions were optimized at a doping concentration of 3.0E15 and an energy of 160 keV.