• Title/Summary/Keyword: chip bonding

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Vibration Analysis of ultrasonic Horn for Flip-Chip Bonding (플립칩 접합용 초음파 혼의 진동해석)

  • Kim, Il-Kwang;Hong, Sang-Hyuk;Lee, Soo-Il
    • Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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    • 2008.11a
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    • pp.364-367
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    • 2008

  • Finite element model and the basic experimental method have been developed to help the design of the transverse ultrasonic horn for flip-chip bonding. With two types of design the horn performance and ultrasonic characteristics are verified by using laser vibrometer. These analysis and experiment results can be the fundamental data for ultrasonic horn design considering the vibration modes and performance.

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High Integration Packaging Technology for RF Application

  • Lee, Young-Min
    • Proceedings of the International Microelectronics And Packaging Society Conference
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    • 1999.12a
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    • pp.127-154
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    • 1999

  • Interconnect - Wire bonding-> Flip chip interconnect ; At research step, Au stud bump bonding seems to be more proper .Package -Plastic package-> $Z_{0}$ controlled land grid package -Flip Chip will be used for RF ICs and CSP for digital ICs -RF MCM comprised of bare active devices and integrated passive components -Electrical design skills are much more required in RF packaging .Passive Component -discrete-> integrated -Both of size and numbers of passive components must be reduced

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Electromigration and Thermomigration in Flip-Chip Joints in a High Wiring Density Semiconductor Package

  • Yamanaka, Kimihiro
    • Journal of the Microelectronics and Packaging Society
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    • v.18 no.3
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    • pp.67-74
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    • 2011

  • Keys to high wiring density semiconductor packages include flip-chip bonding and build-up substrate technologies. The current issues are the establishment of a fine pitch flip-chip bonding technology and a low coefficient of thermal expansion (CTE) substrate technology. In particular, electromigration and thermomigration in fine pitch flipchip joints have been recognized as a major reliability issue. In this paper, electromigration and thermomigration in Cu/Sn-3Ag-0.5Cu (SAC305)/Cu flip-chip joints and electromigration in Cu/In/Cu flip chip joints are investigated. In the electromigration test, a large electromigration void nucleation at the cathode, large growth of intermetallic compounds (IMCs) at the anode, a unique solder bump deformation towards the cathode, and the significantly prolonged electromigration lifetime with the underfill were observed in both types of joints. In addition, the effects of crystallographic orientation of Sn on electromigration were observed in the Cu/SAC305/Cu joints. In the thermomigration test, Cu dissolution was accelerated on the hot side, and formation of IMCs was enhanced on the cold side at a thermal gradient of about $60^{\circ}C$/cm, which was lower than previously reported. The rate of Cu atom migration was found comparable to that of electromigration under current conditions.

  • https://doi.org/10.6117/kmeps.2011.18.3.067 인용 PDF KSCI

Critical Cleaning Requirements for Flip Chip Packages

  • Bixenman, Mike;Miller, Erik
    • Proceedings of the International Microelectronics And Packaging Society Conference
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    • 2000.04a
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    • pp.43-55
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    • 2000

  • In traditional electronic packages the die and the substrate are interconnected with fine wire. Wire bonding technology is limited to bond pads around the peripheral of the die. As the demand for I/O increases, there will be limitations with wire bonding technology. Flip chip technology eliminates the need for wire bonding by redistributing the bond pads over the entire surface of the die. Instead of wires, the die is attached to the substrate utilizing a direct solder connection. Although several steps and processes are eliminated when utilizing flip chip technology, there are several new problems that must be overcome. The main issue is the mismatch in the coefficient of thermal expansion (CTE) of the silicon die and the substrate. This mismatch will cause premature solder Joint failure. This issue can be compensated for by the use of an underfill material between the die and the substrate. Underfill helps to extend the working life of the device by providing environmental protection and structural integrity. Flux residues may interfere with the flow of underfill encapsulants causing gross solder voids and premature failure of the solder connection. Furthermore, flux residues may chemically react with the underfill polymer causing a change in its mechanical and thermal properties. As flip chip packages decrease in size, cleaning becomes more challenging. While package size continues to decrease, the total number of 1/0 continue to increase. As the I/O increases, the array density of the package increases and as the array density increases, the pitch decreases. If the pitch is decreasing, the standoff is also decreasing. This paper will present the keys to successful flip chip cleaning processes. Process parameters such as time, temperature, solvency, and impingement energy required for successful cleaning will be addressed. Flip chip packages will be cleaned and subjected to JEDEC level 3 testing, followed by accelerated stress testing. The devices will then be analyzed using acoustic microscopy and the results and conclusions reported.

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