• Journal of the Microelectronics and Packaging Society
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• v.7 no.1
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• pp.51-59
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• 2000

As integrated circuits become more complex, the number of I/O connections per chip grow. Conventional wire-bonding, lead-frame mounting techniques are unable to keep up. The space saved by shrinking die size is lost when the die is packaged in a huge device with hundreds of leads. The solution is bumps; gold, conductive adhesive, but most importantly solder bumps. Virtually every semiconductor manufacturer in the world is using or planning to use bump technology for their larger and more complex devices. Several wafer-bumping processes used in the manufacture of bumped wafer. Some of the more popular techniques are evaporative, stencil or screen printing, electroplating, electroless nickel, solder jetting, stud humping, decal transfer, punch and die, solder injection or extrusion, tacky dot process and ball placement. This paper will discuss the process steps for bumping wafers using these techniques. Critical cleaning is a requirement for each of these processes. Key contaminants that require removal are photoresist and flux residue. Removal of these contaminants requires wet processes, which will not attack, wafer metallization or passivation. Research has focused on enhanced cleaning solutions that meet this critical cleaning requirement. Process parameters defining time, temperature, solvency and impingement energy required to solvate and remove residues from bumped wafers will be presented herein.

• Journal of the Microelectronics and Packaging Society
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• v.21 no.3
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• pp.1-6
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• 2014

The demand for fine-pitch devices is increasing due to an increase in I/O pin count, a reduction in power consumption, and a miniaturization of chip and package. In addition non-scalability of Cu pillar/Sn cap or Pb-free solder structure for fine-pitch interconnection leads to the development of bumpless interconnection system. Few bumpless interconnect systems such as BBUL technology, SAB technology, SAM technology, Cu-toCu thermocompression technology, and WOW's bumpless technology using an adhesive have been reviewed in this paper: The key requirements for Cu bumpless technology are the planarization, contamination-free surface, and surface activation.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2002.10a
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• pp.536-539
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• 2002

In this paper, we developed the automatic optical fiber aligner by image processing and automatic loading system. Optical fiber is indispensable for optical communication systems that transmit large volumes of data at high speed, but super-precision technology in sub-micron units is required for optical axis adjustment, we have developed 6-axis micro stage system for I/O optical fiber arrays, the initial automatic aligning system/software for a input optical array by the image processing technique, fast I/O-synchronous aligning strategy, the automatic loading/unloading system and the automatic UV bonding mechanism. In order to adjust the alignment it used on PC based motion controller, a $10\mu\textrm{mm}$ repeat-detailed drawing of automatic loading system is developed by a primary line up for high detailed drawing. Also, at this researches used the image processing system and algorithm instead of the existing a primary hand-line up. and fiber input array and waveguide chip formed in line by automatic. Therefore, the developed and manufactured optical aligning system in this research fulfills the great role of support industry for major electronics manufacturers, telecommunications companies, universities, government agencies and other research institutions.

• Journal of the Optical Society of Korea
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• v.13 no.4
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• pp.434-438
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• 2009

In this paper, a 12.5-Gb/s optical transmitter is implemented using 0.13-${\mu}m$ CMOS technology. The optical transmitter that we constructed compensates temperature effects of VCSEL (Vertical cavity surface emitting laser) using auto-power control (APC) and auto-modulation control (AMC). An external monitoring photodiode (MPD) detects optical power and modulation. The proposed APC and AMC demonstrate 5$\sim$20-mA of bias-current control and 5$\sim$20-mA of modulation-current control, respectively. To enhance the bandwidth of the optical transmitter, an active feedback amplifier with negative capacitance compensation is exploited. The whole chip consumes only 140.4-mW of DC power at a single 1.8-V supply under the maximum modulation and bias currents, and occupies the area of 1280-${\mu}m$ by 330-${\mu}m$ excluding bonding pads.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.05c
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• pp.204-207
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• 2003

The flip chip bonding utilizing self-aligning characteristic of solder becomes mandatory to meet to tolerances for the optical device. In this paper, a parametric study of aging condition and pad size of sample was conducted. A TiW/Cu UBM structure was adopted and sample was aging treated to analyze the effect of intermetallic compound with time variation. After aging treatment, the tendency to decrease in shear strength was measured and the structure of the fine joint area was observed by using SEM, TEM and EDS. In result, the shear strength was decreased of about 20% in the $100{\mu}m$ sample at $170^{\circ}C$ aging compared with the maximum shear strength of same pad size sample. In the case of the $120^{\circ}C$ aging treatment, 17% of decrease in shear strength was measured at the $100{\mu}m$ pad size sample. Also, intremetallic compound of $Cu_6Sn_5$ and $Cu_3Sn$ were observed through the TEM measurement by using an FIB technique that is very useful to prepare TEM thin foil specimens from the solder joint interface.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.27 no.9
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• pp.1-5
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• 2013

We developed high-efficient 6W-LED package with simple structure by applying Heat Slug and silicone-reflector. LED package was manufactured in $8.5{\times}8.5mm$ sized multi-chip structure having thickness of $500{\mu}m$ achieved by bonding silicon-reflector with prepreg on top of the plate after implementing the reflector placed on copper substrate Half Etching by thickness of $200{\mu}m$. The luminous flux, luminous efficacy, correlated color temperature, color rendering index and thermal resistance of developed LED was evaluated, and it verified the application of products by applying it to 120W-LED road luminaires through simulation. The luminous efficacy of LED package reached over 130lm/W, and it is possible to be manufactured into 120W-LED road luminaires using 18 packages. In addition, the simulation results showed average of horizontal illuminance and overall illuminance uniformity that is suitable for three-lane road.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.20 no.10
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• pp.112-118
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• 2021

In this study, an inspection method using a color image is proposed to conduct a real-time inspection of covalent organic framework (COF) films to detect defects, if any. The COF film consists of an upper pattern SR and a lower PI. The proposed system detects the defects of more than 20 ㎛ on the SR surface owing to the characteristics of the pattern, whereas on the PI surface, it detects defects of more than 4 ㎛ by utilizing a micro-optical system. In the existing system, it is difficult for the operator to conduct a full inspection through a high-performance microscope. The proposed inspection algorithm performs the inspection by separating each color component using the color contrast of the pattern on the SR side, and on the PI surface it inspects the bonding state of the mounted chip. As a result, it is possible to confirm the exact location of the defects through the SR and PI surface inspections in the implemented inspection.

• Journal of Sensor Science and Technology
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• v.31 no.6
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• pp.361-365
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• 2022

Advanced packaging demands are driven by the need for dense integration systems. Consequently, stacked packaging technology has been proposed instead of reducing the ultra-fine patterns to secure economic feasibility. This study proposed an effective packaging process technology for semiconductor devices using a 9-inch dicing die attach film (DDAF), wherein the die attach and dicing films were combined. The process involved three steps: tape lamination, dicing, and bonding. Following the grinding of a silicon wafer, the tape lamination process was conducted, and the DDAF was arranged. Subsequently, a silicon wafer attached to the DDAF was separated into dies employing a blade dicing process with a two-step cut. Thereafter, one separated die was bonded with the other die as a substrate at 130 ℃ for 2 s under a pressure of 2 kgf and the chip was hardened at 120 ℃ for 30 min under a pressure of 10 kPa to remove air bubbles within the DAF. Finally, a curing process was conducted at 175 ℃ for 2 h at atmospheric pressure. Upon completing the manufacturing processes, external inspections, cross-sectional analyses, and thermal stability evaluations were conducted to confirm the optimality of the proposed technology for application of the DDAF. In particular, the shear strength test was evaluated to obtain an average of 9,905 Pa from 17 samples. Consequently, a 3D integration packaging process using DDAF is expected to be utilized as an advanced packaging technology with high reliability.

• Journal of the Microelectronics and Packaging Society
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• v.8 no.4
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• pp.11-15
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• 2001

In this paper, hermetic sealing technology was studied for wafer level packaging of the RF-MEMS devices. With the flip-chip bonding method. this non-conductive B-stage epoxy sealing will be profit to the MEMS device sealing. It will be particularly profit to the RF-MEMS device sealing. B-stage epoxy can be cured by 2-step and hermetic sealing can be obtained. After defining 500 $\mu\textrm{m}$-width seal-lines on the glass cap substrate by screen printing, it was pre-baked at $90^{\circ}C$ for about 30 minutes. It was, then, aligned and bonded with device substrate followed by post-baked at $175^{\circ}C$ for about 30 minutes. By using this 2-step baking characteristic, the width and the height of the seal-line could be maintained during the sealing process. The height of the seal-line was controlled within $\pm$0.6 $\mu\textrm{m}$ in the 4 inches wafer and the bonding strength was measured to about 20MPa by pull test. The leak rate, that is sealing characteristic of the B-stage epoxy, was about $10^{-7}$ cc/sec from the leak test.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.1
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• pp.47-53
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• 2012

Bonding strength of Sn-3.0Ag-0.5Cu solder joint due to degradation characteristic of OSP surface finish was investigated, compared with SnPb finish. The thickness variation and degradation mechanism of organic solderability preservative(OSP) coating were also analyzed with the number of reflow process. To analyze the degradation degree of solder joint strength, FR-4 PCB coated with OSP and SnPb were experienced preheat treatment as a function of reflow number from 1st to 6th pass, respectively. After 2012 chip resistors were soldered with Sn-3.0Ag-0.5Cu on the pre-heated PCB, the shear strength of solder joints was measured. The thickness of OSP increased with increase of the number of reflow pass by thermal degradation during the reflow process. It was also observed that the preservation effect of OSP decreased due to OSP degradation which led Cu pad oxidation. The mean shear strength of solder joints formed on the Cu pads finished with OSP and SnPb were 58.1 N and 62.2 N, respectively, through the pre-heating of 6 times. Although OSP was degraded with reflow process, the feasibility of its application was proven.