• IEIE Transactions on Smart Processing and Computing
• /
• v.4 no.5
• /
• pp.297-304
• /
• 2015

A multilayer gaseous detector has been developed for fast dose-verification measurements of raster-scan-mode therapeutic beams in particle therapy. The detector, which was constructed with eight thin parallel-plate ionization chambers (PPICs) and polymethyl methacrylate (PMMA) absorber plates, is closely tissue-equivalent in a beam's eye view. The gas-electron signals, collected on the strips and pad arrays of each PPIC, were amplified and processed with a continuous charge.integration mode. The detector was tested with 190-MeV raster-scan-mode beams that were provided by the Proton Therapy Facility at Samsung Medical Center, Seoul, South Korea. The detector responses of the PPICs for a 190-MeV raster-scan-mode proton beam agreed well with the dose data, measured using a 2D ionization chamber array (Octavius model, PTW). Furthermore, in this study it was confirmed that the detector simultaneously tracked the doses induced at the PPICs by the fast-oscillating beam, with a scanning speed of 2 m s-1. Thus, it is anticipated that the present detector, composed of thin PPICs and operating in charge.integration mode, will allow medical scientists to perform reliable fast dose-verification measurements for typical dynamic mode therapeutic beams.

• Nuclear Engineering and Technology
• /
• v.52 no.7
• /
• pp.1503-1510
• /
• 2020

Ultra-low noise charge sensitive amplifiers (CSAs) based on various types of circuit board substrates, such as FR4, Teflon, and ceramics (Al₂O₃) with two different designs, PA1 and PA2, have been developed. They were tested to see the noise effect from the dielectric loss of the substrate capacitance before and after irradiation. If the electronic noise from the CSAs is to be minimized and the energy resolution enhanced, the shaping time has to be optimized for the detector, and a small feedback capacitance of the CSA is favorable for a better SNR. Teflon- and ceramic-based PA1 design CSAs showed better noise performance than the FR4-based one, but the Teflon-based PA1 design showed better sensitivity than ceramic based one at a low detector capacitance (<10 pF). In the PA2 design, the equivalent noise and the sensitivity were 0.52 keV FWHM for a silicon detector and 7.2 mV/fC, respectively, with 2 ㎲ peaking time and 0.1 pF detector capacitance. After 10, 100, 10³, 10⁴, and 10⁵ Gy irradiation the ENC and sensitivity characteristics of the developed CSAs based on three different substrate materials are also discussed.

• Proceedings of the KSRS Conference
• /
• 2003.11a
• /
• pp.1121-1123
• /
• 2003

The CCD (Charge coupled device) detector that is used to convert the light into electronic data is very important component in satellite camera. A Linear CCD Spectral detector shall be used in the MSC (Multi-Spectral Camera, to obtain data for high-resolution images) Payload. In this paper, the design concept of the CCD detector control module in the MSC CEU (Camera electronic unit) system which will be a payload on KOMPSAT is described in terms of H/W (clock speed and accuracy).

• Bulletin of the Korean Space Science Society
• /
• 2004.04a
• /
• pp.100-100
• /
• 2004

Silicon Charge Detector is to measure the charge of incident cosmic-ray nuclei with a resolution of 0.2 charge unit for atomic number, Z=1-30 with energy range from 1 to 1000 TeV. It is one of detectors for CREAM (Cosmic Ray Energetics And Mass) experiment to test current models of source and acceleration mechanisms of ultra high energy cosmic rays. It's first flight will be with a NASA zero pressure balloon planned to be launched from McMurdo Station, Antarctica in December 2004. (omitted)

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.14 no.2
• /
• pp.198-201
• /
• 2014

The phase frequency detector (PFD) is one of the most important building blocks of a phase locked Loop (PLL). Due to blind-zone problem, the detection range of the PFD is low. The blind zone of a PFD directly depends upon the reset time of the PFD and the pre-charge time of the internal nodes of the PFD. Taking these two parameters into consideration, a PFD is designed to achieve a small blind zone closer to the limit imposed by process-voltage-temperature variations. In this paper an enhanced architecture is proposed for dynamic logic PFD to minimize the blind-zone problem. The techniques used are inverter sizing, transistor reordering and use of pre-charge transistors. The PFD is implemented in 180 nm technology with supply voltage of 1.8 V.

• Proceedings of the Korean Nuclear Society Conference
• /
• 1995.05a
• /
• pp.973-979
• /
• 1995

The input equivalent noise charge (ENC) of hydrogenated amorphous silicon radiation detector diodes was measured and analyzed. The noise sources of amorphous silicon diodes were analyzed into three sources; shot noise, flicker noise and thermal noise from the contact resistance. By comparing the measured ENC with the calculated signal charge in uniform generation case, the signal-to-noise ratio (S/N) for the sample diodes is estimated as a function of the detector bias and the shaping time of Gaussian pulse shaper. The maximum S/N occurred at the bias level just above the full depletion voltage for shaping time of 2∼3 ${\mu}$sec. The developed method is useful in optimum design or amorphous silicon p-i-n diodes for charged particulate radiation spectroscopy.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2003.11a
• /
• pp.388-391
• /
• 2003

The properties of these detectors can be controlled by electronics and exposure conditions. Flat-panel detectors for digital diagnostic imaging convert incident x-ray images to charge images. Flat panel detectors gain more interest real time medical x-ray imaging. Active area of flat panel detector is $14{\times}17$ inch. Detector is based on a $2560{\times}3072$ away of photoconductor and TFT pixels. X-ray conversion layer is deposited upper TFT array flat panel with a 500m by thermal deposition technology. Thickness uniformity of this layer is made of thickness control technology(5%) of thermal deposition system. Each $139m{\times}139m$ pixel is made of thin film transistor technology, a storage capacitor and charge collection electrode having geometrical fill factor of 86%. Using the separate driving system of two dimensional mosaic modules for large area, that is able to 4.2 second per frame. Imaging performance is suited for digital radiography imaging substitute by conventional radiography film system..

• Proceedings of the IEEK Conference
• /
• 2003.07b
• /
• pp.963-966
• /
• 2003

This paper proposes a new locking algorithm of the delay locked loop (DLL) which reduces the lock-acquisition time and eliminates false locking problem to enlarge the operating frequency range. The proposed DLL uses the modified phase frequency detector (MPFD) and the modified charge pump (MCP) to avoid the false locking problem. Adopting a new lock detector that measures delay between elects helps the fast lock-acquisition time greatly. The idea has been confirmed by HSPICE simulations in a 0.35-${\mu}{\textrm}{m}$ CMOS process.

• The Transactions of the Korean Institute of Electrical Engineers D
• /
• v.50 no.10
• /
• pp.479-485
• /
• 2001

In this paper, we introduce a charge pump phase-locked loop (PLL) architecture which employs a precharge phase frequency detector (PFD) and a sequential PFD to achieve a high frequency operation and a fast acquisition. Operation frequency is increased by using the precharge PFD when the phase difference is within $-{\pi}{\sim}{\pi}$ and acquisition time is shortened by using the sequential PFD and the increased charge pump current when the phase difference is larger than ${\pm}{\pi}$. So error detection range of the proposed PLL structure is not limited to $-{\pi}{\sim}{\pi}$ and a high frequency operation and a higher speed lock-up time can be achieved. The proposed PLL was designed using 1.5 ${\mu}m$ CMOS technology with 5V supply voltage to verify the lock in process. The proposed PLL shows successful acquisition for 200 MHz input frequency. On the other hand, the conventional PLL with the sequential PFD cannot operate at up to 160MHz. Moreover, the lock-up time is drastically reduced from 7.0 ${\mu}s\;to\;2.0\;{\mu}s$ only if the loop bandwidth to input frequency ratio is regulated by the divide-by-4 counter during the acquisition process. By virtue of this dual PFDs, the proposed PLL structure can improve the trade-off between acquisition behavior and locked behavior.

• Bulletin of the Korean Space Science Society
• /
• 2005.10a
• /
• pp.44-44
• /
• 2005