• Title/Summary/Keyword: channel reliability

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Effects of omni channel characteristics on consumers' perceived risk, attitude, and intention (옴니채널(Omni Channel) 특성이 소비자들의 지각된 위험과 태도 및 이용의도에 미치는 영향)

  • Hong, Jung-min;Shin, Su-yun
    • The Research Journal of the Costume Culture
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    • v.26 no.3
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    • pp.346-359
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    • 2018
  • Currently, dramatic change had led to the growth of the distribution environment and the retailer's distribution channel. This change had shifted the 'single channel' to 'multi channel', and from 'cross channel' to 'omni channel'. While fashion companies using omni channel are rapidly growing, few research regarding omni channel had been done in academic field. In this study, we examined the influence of omni channel characteristics on consumers' perceived risk as well as consumers' perceived risk toward attitude and intention to use omni channel. We surveyed 696 male and female respondents aged 20 to 40 who lived in Seoul and the metropolitan area. Using AMOS 20.0, factor analysis, reliability analysis, and structural equation model analysis were performed to verify the model of this study. The results were as follows. First, omni channel's instant connectivity, location-based provability, interactivity, and entertainment factors did not decrease impacts on the perceived risk related to privacy and annoyance. Second, omni channel's instant connectivity and entertainment did not increase effects on the perceived financial risk, and location-based provability and interactivity did not increase effect on perceived financial risk. Third, the perceived risk concerning omni channel did not decrease on consumer attitude toward omni channel. Fourth, consumer attitude toward omni channel influenced the intention to use omni channel significantly.

MIMO Channel Diagonalization: Linear Detection ZF, MMSE (MIMO 채널 대각화: 선형 검출 ZF, MMSE)

  • Yang, Jae Seung;Shin, Tae Chol;Lee, Moon Ho
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.16 no.1
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    • pp.15-20
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    • 2016
  • Compared to the MIMO system using the spatial multiplexing methods and the MIMO system using the diversity scheme achieved a high rate, but the lower the diversity gain to improve the data transmission reliability should separate the spatial stream at the MIMO receiver. In this paper, we compared Channel capacity detection methods with the Lattice code, the 3-user interference channel and linear channel interference detection methods ZF (Zero Forcing) and MMSE (Minimum Mean Square Error) detection methods. The channel is a Diagonal channel. In other words, Diagonal channel is confirmed by the inverse matrix satisfies the properties of Jacket are element-wise inverse to $[H]_N[H]_N^{-1}=[I]_N$.

EPC C1 Gen2 RFID System with Channel Coding (채널 부호를 적용한 EPC C1 Gen2 RFID 시스템)

  • Jeon, Ki-Yong;Cho, Sung-Ho
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.33 no.2A
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    • pp.174-182
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    • 2008
  • For the UHF EPC C1 Gen2 RFID system, to overcome the performance degradation in wireless channel environments, we proposed a modified tag structure which supports channel coding and its applied methodology. The reader consistently monitors the wireless channel status and sets to use channel coding functions for tags and reader only if wireless channel is corrupted. Compared with previous tag complexity, only negligible gates are needed to implement channel coding. By simulation we showed an obvious performance improvement of the identification reliability.

Optimization of InAlAs/InGaAs HEMT Performance for Microwave Frequency Applications and Reliability

  • Gupta, Ritesh;Aggarwal, Sandeep Kumar;Gupta, Mridula;Gupta, R.S.
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.4 no.3
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    • pp.240-249
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    • 2004
  • In the present paper efforts have been made to optimize InAlAs/InGaAs HEMT by enhancing the effective gate voltage ($(V_c-V_off)$) using pulsed doped structure from uniformly doped to delta doped for microwave frequency applications and reliability. The detailed design criteria to select the proper design parameters have also been discussed in detail to exclude parallel conduction without affecting the del ice performance. Then the optimized value of $V_c-V_off$and breakdown voltages corresponding to maximum value of transconductance has been obtained. These values are then used to predict the transconductance and cut-off frequency of the del ice for different channel depths and gate lengths.

Delay Time Reliability of Analog and Digital Delay Elements for Time-to-Digital Converter

  • Choi, Jin-Ho
    • Journal of information and communication convergence engineering
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    • v.8 no.1
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    • pp.103-106
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    • 2010
  • In this paper, the delay times were evaluated to develop highly reliable time-to-digital converter(TDC) in analog and digital delay element structures. The delay element can be designed by using current source or inverter. In case of using inverter, the number of inverter has to be controlled to adjust the delay time. And in case of using current source, the current for charging and discharging is controlled. When the current source is used the delay time of the delay element is not sensitive with varying the channel width of CMOS. However, when the inverter is used the delay time is directly related to the channel width of CMOS. Therefore to obtain good reliability in TDC circuit the delay element using current source is more stable compared to inverter in the viewpoint of the variation of fabrication process.

Nanoscale NAND SONOS memory devices including a Seperated double-gate FinFET structure

  • Kim, Hyun-Joo;Kim, Kyeong-Rok;Kwack, Kae-Dal
    • Journal of Applied Reliability
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    • v.10 no.1
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    • pp.65-71
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    • 2010
  • NAND-type SONOS with a separated double-gate FinFET structure (SDF-Fin SONOS) flash memory devices are proposed to reduce the unit cell size of the memory device and increase the memory density in comparison with conventional non volatile memory devices. The proposed memory device consists of a pair of control gates separated along the direction of the Fin width. There are two unique alternative technologies in this study. One is a channel doping method and the other is an oxide thickness variation method, which are used to operate the SDF-Fin SONOS memory device as two-bit. The fabrication processes and the device characteristics are simulated by using technology comuter-adided(TCAD). The simulation results indicate that the charge trap probability depends on the different channel doping concentration and the tunneling oxide thickness. The proposed SDG-Fin SONOS memory devices hold promise for potential application.

Poly-Si TFT LCD using p-channel TFTs

  • Ha, Yong-Min;Park, Jae-Deok;Yeo, Ju-Cheon;Kim, Dong-Gil
    • 한국정보디스플레이학회:학술대회논문집
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    • 2000.01a
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    • pp.153-154
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    • 2000
  • Large size poly-Si TFT-LCDs have been fabricated using p-channel thin film transistors for notebook PC application. We have designed and implemented the data sampling circuit and gate drivers that operate with low power consumption and high reliability. The gate driver has a redundant structure. We have realized the uniform and excellent display quality comparable to that of CMOS module. The reliability of panel is investigated and discussed by measuring the bias stability of transistors.

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An Efficient Method that Incorporate a Channel Reliability to the Log-MAP-based Turbo Decoding (Log-MAP 방식의 Turbo 복호를 위한 효과적인 채널 신뢰도 부과방식)

  • 고성찬;정지원
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.25 no.3B
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    • pp.464-471
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    • 2000
  • The number of quantization bits of the input signals $X_k$,$Y_k$ need to be optimally determined through the trade-off between the H/W complexity and the BER performance in Turbo codes applications. Also, an effective means to incorporate a channel reliability $L_c$ in the Log-MAP-based Turbo decoding is highly required. because it has a major effect on both the complexity and the performance. In this paper, a novel bit-shifting approach that substitutes for the multiplying is proposed so as to effectively incorporate. $L_c$ in Turbo decoding. The optimal number of quantization bits of $X_k$,$Y_k$ is investigated through Monte-Carlo simulations assuming that bit-shifting approach is adopted. In addition. The effects of an incorrect estimation of noise variance on the performance of Turbo codes is investigated. There is a confined range in which the effects of an incorrect estimation can be ignored.

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Channel Modeling and RF Performance Verification in mmWave Bands Based on NS-3 (NS-3 기반의 mmWave 대역 채널 모델링 및 RF 성능 검증)

  • Seung-Min Lee;Jun-Seok Seo;Hong-Je Jang;Myung-Ryul Choi
    • Journal of IKEEE
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    • v.27 no.4
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    • pp.650-656
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    • 2023
  • This paper implements a channel model for mmWave bands using an NS-3-based 5G system-level simulator and analyzes the reliability and validity of the implemented model through RF performance verification. The channel model for RF performance verification in the mmWave bands consider parameters such as characteristics defined in 3GPP TR 38.901, beam-forming, antenna configuration, scenarios, among others. Furthermore, the simulation results verify compliance within the ranges permitted by the 3GPP standards and verify reliability in indoor environmental scenarios by exploiting the Radio Environment Map (REM). Therefore, the channel model implemented in this study is applicable to the actual design and establishment of 5G networks, presenting a method to evaluate and validate RF performance by adjusting various parameters.

Effects of Doping Concentration of Polycrystalline Silicon Gate Layer on Reliability Characteristics in MOSFET's (MOSFET에서 다결정 실리콘 게이트 막의 도핑 농도가 신뢰성에 미치는 영향)

  • Park, Keun-Hyung
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.31 no.2
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    • pp.74-79
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    • 2018
  • In this report, the results of a systematic study on the effects of polycrystalline silicon gate depletion on the reliability characteristics of metal-oxide semiconductor field-effect transistor (MOSFET) devices were discussed. The devices were fabricated using standard complimentary metal-oxide semiconductor (CMOS) processes, wherein phosphorus ion implantation with implant doses varying from $10^{13}$ to $5{\times}10^{15}cm^{-2}$ was performed to dope the polycrystalline silicon gate layer. For implant doses of $10^{14}/cm^2$ or less, the threshold voltage was increased with the formation of a depletion layer in the polycrystalline silicon gate layer. The gate-depletion effect was more pronounced for shorter channel lengths, like the narrow-width effect, which indicated that the gate-depletion effect could be used to solve the short-channel effect. In addition, the hot-carrier effects were significantly reduced for implant doses of $10^{14}/cm^2$ or less, which was attributed to the decreased gate current under the gate-depletion effects.