• 대한기계학회:학술대회논문집
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• 대한기계학회 2008년도 추계학술대회B
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• pp.2658-2663
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• 2008

In the present study, we designed a microfluidic flatform that generates monodisperse droplets with diameters ranging from hundreds of nanometers to several micrometers. To generate fine droplets, T-junction and flow-focusing geometry are integrated into the microfluidic channel. Relatively large aqueous droplets are generated at the upstream T-junction and transported toward the flow-focusing geometry, where each droplet is broken up into the targeted size by the action of viscous stresses. Because the droplet prior to rupture blocks the straight channel that leads to the flow-focusing geometry, it moves very slowly by the pressure difference applied between the advancing and receding regions of the moving droplet. This configuration enables very low flow rate of inner fluid and higher flow rate ratio between inner and outer fluids at the flow-focusing region. It is shown that the present microfluidic device can generate droplets with diameters about 1 micrometer size and standard deviation less than 3%.

• JSTS:Journal of Semiconductor Technology and Science
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• 제7권2호
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• pp.82-87
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• 2007

The electrical properties of metallic junction diodes and metallic source/drain (S/D) Schottky barrier metal-oxide-semiconductor field-effect transistor (SB-MOSFET) were simulated. By using the abrupt metallic junction at the S/D region, the short-channel effects in nano-scaled MOSFET devices can be effectively suppressed. Particularly, the effects of trap states at the metal-silicide/silicon interface of S/D junction were simulated by taking into account the tail distributions and the Gaussian distributions at the silicon band edge and at the silicon midgap, respectively. As a result of device simulation, the reduction of interfacial trap states with Gaussian distribution is more important than that of interfacial trap states with tail distribution for improving the metallic junction diodes and SB-MOSFET. It is that a forming gas annealing after silicide formation significantly improved the electrical properties of metallic junction devices.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 추계학술대회 논문집 Vol.19
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• pp.133-134
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• 2006

A simple doping method to fabricate a very thin channel body of the n-type fin field-effect-transistor (FinFET) with a 20 nm gate length by solid-phase-diffusion (SPD) process is presented. Using As-doped spin-on-glass as a diffusion source of arsenic and the rapid thermal annealing, the n-type source-drain extensions with a three-dimensional structure of the FinFET devices were doped. The junction properties of arsenic doped regions were investigated by using the $n^+$-p junction diodes which showed excellent electrical characteristics. Single channel and multi-channel n-type FinFET devices with a gate length of 20-100 nm was fabricated by As-SPD and revealed superior device scalability.

• 한국전산유체공학회:학술대회논문집
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• 한국전산유체공학회 2008년도 춘계학술대회논문집
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• pp.2-5
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• 2008

This study describes the numerical simulation of three-dimensional droplet formation and the following motion in a cross-junction microchannel by using the Lattice Boltzmann Method (LBM). Our aim is to develop the three-dimensional binary fluids model, consisting of two sets of distribution functions to represent the total fluid density and the density difference, which introduces the repulsive interaction consistent with a free-energy function between two fluids. We validated the LBM code with the velocity profile in a 3-dimensional rectangular channel. Then, we applied our code to the numerical simulation of a binary fluid flow in a cross-junction channel focusing on the investigation of the droplet formulation. Due to the pressure and interfacial-tension effect, one component of the fluids which is injected from one inlet is cut off into many droplets periodically by the other component which is injected from the other inlets. We considered the effect of the boundary conditions for density difference (order parameter) on the wetting of the droplet to the side walls.

• 대한전자공학회논문지
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• 제27권9호
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• pp.1409-1418
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• 1990

Characteristics of NMOS transistors with phosphorus source/drain junctions formed by two-step rapid thermal diffusion (RTD) process using a solid diffusion source have been investigated. Phosphorus profiles after RTD were measured by SIMS analysis. In the case of 1100\ulcorner, 10sec RTD of, P, the specific contact resistance of n+ Si-Al was 2.4x10**-7 \ulcorner-cm\ulcorner which is 1/5 of the As junction The comparison fo P junction devices formed by RTD and conventional As junction devices shows that both short channel effect and hot carrier effect of P junction devices are smaller than those of As junction devices when the devices have same junction depths. P junction device had maximum of 0.4 times lower Isub/Id than As junction device. Characteristics of P junction formed by several different RTD conditions have been compared and 1000\ulcorner RTD sample had the smaller hot carrier generation. Also, it has been shown that the hot carrier generation can be futher reduced by forming the P junctions by 3-step RTD which has RTO-driven-in process additionally.

• 한국수자원학회논문집
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• 제31권5호
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• pp.529-538
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• 1998

개수로 합류부의 흐름양상이 2차원 수심적분 수학적 모형에 의하여 해석된다. 합류부 흐름에 지배적인 매개변수는 지류와 합류후 유량의 비와 합류각으로 나타났다. 이들 인자의 항으로 해석되는 대상은 합류부에서 흐름양상과 수심의 변화, 본류에서 합류부 상류흐름이 영향을 받기 시작하는 유량비 및 순환영역의 기하특성이다. 또한 합류하류에서 흐름수축과 지류의 굽음각이 조사되었다. 수치해석결과는 기존 실험자료와 비교적 잘 맞는것으로 나타났다.

• 한국전기전자재료학회논문지
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• 제32권2호
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• pp.104-109
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• 2019

An analytical threshold voltage model is proposed to analyze the threshold voltage roll-off and drain-induced barrier lowering (DIBL) for a junction-based double-gate (JBDG) MOSFET and a junction-less double-gate (JLDG) MOSFET. We used the series-type potential distribution function derived from the Poisson equation, and observed that it is sufficient to use n=1 due to the drastic decrease in eigenvalues when increasing the n of the series-type potential function. The threshold voltage derived from this threshold voltage model was in good agreement with the result of TCAD simulation. The threshold voltage roll-off of the JBDG MOSFET was about 57% better than that of the JLDG MOSFET for a channel length of 25 nm, channel thickness of 10 nm, and oxide thickness of 2 nm. The DIBL of the JBDG MOSFET was about 12% better than that of the JLDG MOSFET, at a gate metal work-function of 5 eV. It was also found that decreasing the work-function of the gate metal significantly reduces the DIBL.

• BMB Reports
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• 제28권2호
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• pp.184-190
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• 1995

Functional study of the gap junction channel has been hindered by its inaccessibility in situ. Identification of forms of this channel in artificial membrane has been elusive because of the lack of identifying channel physiology. Connexin32 forms gap junction channels between neighboring cells in rat liver. Connexin32 was affinity-purified using a monoclonal antibody and reconstituted into artificial phospholipid vesicles. The reconstituted connexin32 formed channels through the vesicle membrane that were permeable to sucrose (Stokes radius: $5{\AA}$). The permeability to sucrose was reversibly reduced by acidic pH. In addition, the pH effect on the permeability to sucrose fit well with by the Hill's equation (where, n=2.7 and pK=6.7).

• 한국전기전자재료학회논문지
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• 제22권11호
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• pp.905-909
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• 2009

The new Junction Field Effect Transistors (JFETs) with Silicon-germanium (SiGe) layers is investigated. This structure uses SiGe layer to prevent out diffusion of boron in the channel region. In this paper, we report electrical properties of SiGe JFET measured under various design parameters influencing the performance of the device. Simulation results show that out diffusion of boron is reduced by the insertion SiGe layers. Because the SiGe layer acts as a barrier to prevent the spread of boron. This proposed JFET, regardless of changes in fabrication processes, accurate and stable cutoff voltage can be controlled. It is easy to maintain certain electrical characteristics to improve the yield of JFET devices.

• JSTS:Journal of Semiconductor Technology and Science
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• 제6권1호
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• pp.43-51
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• 2006

80-nm self-aligned n-and p-channel I-MOS devices were demonstrated by using a novel fabrication method featuring double sidewall spacer, elevated drain structure and RTA process. The fabricated devices showed a normal transistor operation with extremely small subthreshold swing less than 12.2 mV/dec at room temperature. The n- and p-channel I-MOS devices had an ON/OFF current of 394.1/0.3 ${\mu}A$ and 355.4/8.9 ${\mu}A$ per ${\mu}m$, respectively. We also investigated some critical issues in device design such as the junction depth of the source extension region and the substrate doping concentration.