• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2000년도 추계종합학술대회 논문집(2)
• /
• pp.13-16
• /
• 2000

A quantum-wire field effect transistor(QW-FET) using asymmetric double InGaAs channel and Si-delta doped barrier has been fabricated. It exhibited good modulation and saturation characteristic in the range of ${\mu}\textrm{A}$ current level. For estimated channel width of 150nm QW-FET, maximum transconductance was about 400 mS/mm which is higher than a conventional heterostructure FET(HFET) with the same epi-structure.

• 한국정보통신학회논문지
• /
• 제14권10호
• /
• pp.2305-2309
• /
• 2010

본 연구에서는 상단게이트와 하단게이트를 갖는 더블게이트 MOSFET에서 채널길이와 채널두께의 비에 따른 문턱전압의 변화에 대하여 분석하였다. 더블게이트 MOSFET는 두개의 게이트를 가지고 있기 때문에 전류제어 능력이 기존 MOSFET의 두배에 가깝고 나노소자에서 단채널효과를 감소시킬 수 있다는 장점이 있다. MOSFET에서 채널길이와 채널두께는 소자의 크기를 결정하며 단채널효과에 커다란 영향을 미치고 있다. 채널길이가 짧아지면 서 채널두께와의 비에 따라 단채널효과 중 문턱전압의 변화가 크게 영향을 받고 있다. 그러므로 이 연구에서는 DGMOSFET에서 채널길이와 채널두께의 비를 변화시키면서 문턱전압의 변화와 드레인 유기장벽감소현상을 분석할 것이다.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제7권2호
• /
• pp.82-87
• /
• 2007

The electrical properties of metallic junction diodes and metallic source/drain (S/D) Schottky barrier metal-oxide-semiconductor field-effect transistor (SB-MOSFET) were simulated. By using the abrupt metallic junction at the S/D region, the short-channel effects in nano-scaled MOSFET devices can be effectively suppressed. Particularly, the effects of trap states at the metal-silicide/silicon interface of S/D junction were simulated by taking into account the tail distributions and the Gaussian distributions at the silicon band edge and at the silicon midgap, respectively. As a result of device simulation, the reduction of interfacial trap states with Gaussian distribution is more important than that of interfacial trap states with tail distribution for improving the metallic junction diodes and SB-MOSFET. It is that a forming gas annealing after silicide formation significantly improved the electrical properties of metallic junction devices.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
• /
• pp.129-130
• /
• 2008

Polycrystalline silicon (poly-Si) Schottky barrier thin film transistors (SB-TFT) are fabricated by erbium silicided source/drain for n-type SB-TFT. High quality poly-Si film were obtained by crystallizing the amorphous Si film with excimer laser annealing (ELA) or solid phase crystallization (SPC) method. The fabricated poly-Si SB-TFTs have a large on/off current ratio with a low leakage current. Moreover, the electrical characteristics of poly-Si SB TFTs are significantly improved by the additional forming gas annealing in 2 % $H_2/N_2$, because the interface trap states at the poly-Si grain boundaries and at the gate oxide/poly-Si channel decreased.

• 한국전기전자재료학회논문지
• /
• 제22권6호
• /
• pp.462-465
• /
• 2009

Schottky barrier thin film transistors (SB-TFT) on polycrystalline silicon(poly-Si) are fabricated by platinum silicided source/drain for p-type SB-TFT. High quality poly-Si film were obtained by crystallizing the amorphous Si film with excimer laser annealing (ELA) or solid phase crystallization (SPC) method, The fabricated poly-Si SB-TFTs showed low leakage current level and a large on/off current ratio larger than 10), Significant improvement of electrical characteristics were obtained by the additional forming gas annealing in 2% $H_2/N_2$ ambient, which is attributed to the termination of dangling bond at the poly-Si grain boundaries as well as the reduction of interface trap states at gate oxide/poly-Si channel.

• International Journal of Naval Architecture and Ocean Engineering
• /
• 제12권1호
• /
• pp.468-478
• /
• 2020

The wave interaction problem with a vertical slotted breakwater, consisting of impermeable upper, lower parts and a permeable middle part, has been studied theoretically. An analytical model was presented for the estimation of reflection and transmission of monochromatic waves by a slotted breakwater. The far-field solution of the wave scattering involving nonlinear porous boundary condition was obtained using eigenfunction expansion method. The empirical formula for drag coefficient in the near-field, representing energy dissipation across the slotted barrier, was determined by curve fitting of the numerical solutions of 2-D channel flow using CFD code StarCCM+. The theoretical model was validated with laboratory experiments for various configurations of a slotted barrier. It showed that the developed analytical model can correctly predict the energy dissipation caused by turbulent eddies due to sudden contraction and expansion of a slotted barrier. The present paper provides a synergetic approach of the analytical and numerical modelling with minimum CPU time, for better estimation of the hydrodynamic performance of slotted breakwater.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제9권3호
• /
• pp.136-147
• /
• 2009

In this paper we analyze the influence of source/drain (S/D) extension region design for minimizing short channel effects (SCEs) in 25 nm gate length single and double gate Silicon-on-Insulator (SOI) and Germanium-on-Insulator (GOI) MOSFETs. A design methodology, by evaluatingm the ratio of the effective channel length to the natural length for the different devices (single or double gate FETs) and technology (SOI or GOI), is proposed to minimize short channel effects (SCEs). The optimization of non-overlapped gate-source/drain i.e. underlap channel architecture is extremely useful to limit the degradation in SCEs caused by the high permittivity channel materials like Germanium as compared to that exhibited in Silicon based devices. Subthreshold slope and Drain Induced Barrier Lowering results show that steeper S/D gradients along with wider spacer regions are needed to suppress SCEs in GOI single/double gate devices as compared to Silicon based MOSFETs. A design criterion is developed to evaluate the minimum spacer width associated with underlap channel design to limit SCEs in SOI/GOI MOSFETs.

• 한국전산구조공학회:학술대회논문집
• /
• 한국전산구조공학회 2008년도 정기 학술대회
• /
• pp.490-494
• /
• 2008

U-Channel Bridge is effective bridge type, because its edge beam performs role of barrier and enables to reduce additional dead loads. Although it is effective to reduce additional dead loads, there is possibility of bridge collapse under impact load due to car crash. Also, edge beam must have ability to induce safe driving and prevent falling accidents. Therefore, it requires behavior analysis and property investigation through the vehicle impact crashing edge beam. This study presents method of structural analysis of U-channel bridge and investigates design specifications for the effect of the edge beam under the vehicle impact. Also, it carries out stability investigation of behavior of edge beam and slab, based on Korean Highway Bridge Design Specifications and AASHTO LRFD Bridge Design Specification.

• 소음진동
• /
• 제9권6호
• /
• pp.1137-1144
• /
• 1999

Most of ANC(active noise control) researches are focused on adaptive algorithms, computer simulations and implementations of single-channel system in experimental environments. In this paper, a multi-channel ANC system based on DSP's was developed to obtain global attenuations over wide region and applied to the active control of the humming noise generated by a transformer. The developed ANC system including 24 microphones and 12 spearkers was applied to the real transformer noise reduction problem. Results showed that the control system could successfully control the humming noise over the region of interest.

• EDISON SW 활용 경진대회 논문집
• /
• 제4회(2015년)
• /
• pp.357-364
• /
• 2015

In this work, we investigate the quantum effects exhibited from ultra-thin GAA(gate-all-around) Nanowire FETs for Sub 14nm Technology. We face designing challenges particularly short channel effects (SCE). However traditional MOSFET SCE models become invalid due to unexpected quantum effects. In this paper, we investigated various performance factors of the GAA Nanowire FET structure, which is promising future device. We observe a variety of quantum effects that are not seen when large scale. Such are source drain tunneling due to short channel lengths, drastic threshold voltage increase caused by quantum confinement for small channel area, leakage current through thin gate oxide by tunneling, induced source barrier lowering by fringing field from drain enhanced by high k dielectric, and lastly the I-V characteristic dependence on channel materials and transport orientations owing to quantum confinement and valley splitting. Understanding these quantum phenomena will guide to reducing SCEs for future sub 14nm devices.