• Journal of the Korean Data and Information Science Society
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• v.24 no.4
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• pp.815-824
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• 2013

Traditional Pearson chi-squared test is not appropriate for the data collected by the complex sample design. When one uses the traditional Pearson chi-squared test to the complex sample categorical data, it may give wrong test results, and the error may occur not only due to the biased variance estimators but also due to the biased point estimators of cell proportions. In this study, the design based consistent Wald test statistics was derived for k-population homogeneity test, and the traditional Pearson chi-squared test statistics was partitioned into three parts according to the causes of error; the error due to the bias of variance estimator, the error due to the bias of cell proportion estimator, and the unseparated error due to the both bias of variance estimator and bias of cell proportion estimator. An analysis was conducted for empirical results of the relative size of each error component to the Pearson chi-squared test statistics. The second year data from the fourth Korean national health and nutrition examination survey (KNHANES, IV-2) was used for the analysis. The empirical results show that the relative size of error from the bias of variance estimator was relatively larger than the size of error from the bias of cell proportion estimator, but its degrees were different variable by variable.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.55 no.3
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• pp.111-115
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• 2006

We investigated accelerated soft error rate(ASER) in 8M static random access memory(SRAM) cells. The effects on ASER by well structure, operational voltage, and cell transistor threshold voltage are examined. The ASER decreased exponentially with respect to operational voltage. The chips with buried nwell1 layer showed lower ASER than those either with normal well structure or with buried nwell1 + buried pwell structure. The ASER decreased as the ion implantation energy onto buried nwell1 changed from 1.5 MeV to 1.0 MeV. The lower viscosity of the capping layer also revealed lower ASER value. The decrease in the threshold voltage of driver or load transistor in SRAM cells caused the increase in the transistor on-current, resulting in lower ASER value. We confirmed that in order to obtain low ASER SRAM cells, it is necessary to also the buried nwell1 structure scheme and to fabricate the cell transistors with low threshold voltage and high on-current.

• Journal of Korea Society of Industrial Information Systems
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• v.7 no.2
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• pp.1-5
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• 2002

In this paper, a concatenated turbo and BCH coding is proposed for the wireless ATM cell transmission and the bit error rate(BER) and the cell loss ratio(CLR) for the Nosed system is obtained. Turbo code with code rate of 1/2 and BCH code with error correction capability of 5 and 15 bits are used in the simulations. It is shown that the proposed system obtained about 0.2 and 0.4 ㏈ gain over the conventional Turbo code at bit error rate of 0.001. Also the proposed system obtained about 0.1 and 0.2 ㏈ gain over the conventional Turbo code at cell loss rate of 0.01.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.413-416
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• 1998

This paper presents a dAC calibration technique for high resolution and monolithic operation. The calibration technique consists of basic source, current memory cell (C.M) and current substrator. Current memory supplies the error current to basic source. Current substrator extracts the error current from the main source. It is simple and needs no special calibration period. The proposed current cell has high calibration performance and guarantees 100MHz operation.

• Information and Communications Magazine
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• v.32 no.6
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• pp.16-22
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• 2015

NAND flash 메모리의 집적도를 높이기 위한 주요 기술로, 데이터가 저장되는 cell 자체의 크기를 줄여주는 미세 공정화와 cell 당 저장되는 정보량을 늘려주는 멀티-레벨(multi-level)화가 사용되고 있다. 이러한 기술의 적용은 NAND flash 메모리 자체의 오류를 증가시키게 되므로, NAND flash 메모리 기반 데이터 저장 장치의 신뢰성을 높은 수준으로 유지하기 위해서는 우수한 정정 능력을 갖는 ECC(error control code) 를 사용하는 것이 필수적이다. 본고에서는 NAND flash 메모리의 신뢰성 특성과 함께 NAND flash 메모리를 사용하는 데이터 저장 장치에서의 ECC의 응용에 대해서 살펴보고자 한다.

• Journal of the Korean Operations Research and Management Science Society
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• v.31 no.3
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• pp.1-10
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• 2006

In this paper we deal with a cell planning issue arisen in a CDMA based multicast network. In a CDMA based wireless network, a terminal can significantly reduce the bit error rate via the cohesion of data streams from multiple base stations. In this case, multiple base stations have to be operated according to a common time line. The cells whose base stations are operated as such are called soft-combined cells. Therefore, a terminal can take advantage of error rate reduction, if the terminal is in a soft-combined cell and at least one neighboring cell is also soft-combined. However, as soft-combining operation gives heavy burden to the network controller, the limited number of cells can be soft-combined. Our problem us to find a limited number of soft-combined cells such that the benefit of the soft-combining operation is maximized.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.1
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• pp.1-11
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• 1997

We examine the DS/SSMA system which is employing coherent BPSK with RAKE receiver. We adop Nakagami m-distribution as a multipath fading model. First, we analyze the performances of the system in the single cell environment and obtain the other-cell interference according to power control error. And considering the other-cell interference into the analysis of single cell system, we examine the cellular CDMA network. The average BER and outage probability are the figures of merit that characterize the system performance. The required BER, 1E-3, and required outage probability are the figures of merit that characterize the system performance. The requeired BER, 1E-3, and required outage probability, 1% for the voice transmission is considered to acquire the capacity of system.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.14 no.6
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• pp.590-603
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• 1989

In tnis paper, the CRC-CCITT code and primitive polynomial CRC code are selected for analysing error detecting performance. However, general formulas for obtaining the weight distribution of these two CRC codes are not so far dericed. So, a new method for calculating the weight distribution of the shortened cyclic Hamming code is presented and an undetected error probability of these two codes is obtained when used in cell of ATM for broadband ISDN user-network interface. Consequently, we show that CRC code too much does affect its error detection performance. All the computer simulation is performed by IBM PC/AT.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.842-846
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• 2015

In this study, we propose an algorithm of the method of recovering quickly find the location of the error encountered during separate operations in the functional structure of complex digital circuits by mimicking the self-healing function of the cell. By the digital circuit was divided by 9 function block unit of function, proposes a method that It can quickly detect and recover the error position. It was the detection and recovery algorithms for the error location in the digital circuit of a complicated structure and could extended the number of function block for the $3{\times}3$ matrix structure on the digital circuit.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.11
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• pp.2745-2750
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• 2015

Abstract should be placed here In this study, we propose an algorithm of the method of recovering quickly find the location of the error encountered during separate operations in the functional structure of complex digital circuits by mimicking the self-healing function of the cell. By the digital circuit was divided by 9 function block unit of function, proposes a method that It can quickly detect and recover the error position. It was the detection and recovery algorithms for the error location in the digital circuit of a complicated structure and could extended the number of function block for the $3{\times}3$ matrix structure on the dital circuit.