• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 하계종합학술대회 논문집(2)
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• pp.327-330
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• 2004

It is shown that the hot carrier degradation due to enhanced hot holes trapping dominates PMOSFETs lifetime both in thin and thick devices. Moreover, it is found that in 0.13 ${\mu}m$ CMOSFET the PMOS lifetime under CHC (Channel Hot Carrier) stress is lower than the NMOSFET lifetime under DAHC (Drain Avalanche Hot Carrier) stress. Therefore. the interface trap generation due to enhanced hot hole injection will become a dominant degradation factor. In case of thick MOSFET, the degradation by hot carrier is confirmed using charge pumping current method and highly necessary to enhance overall device lifetime or circuit lifetime in upcoming nano-scale CMOS technology.

• Journal of Electrical Engineering and Technology
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• 제9권2호
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• pp.489-500
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• 2014

This paper presents a simple modified unipolar carrier-based pulsewidth modulation (CB-PWM) strategy for the three-level neutral-point-clamped (NPC) voltage source inverter (VSI). Analytical expressions for the relationship between modulation reference signals and output voltages are derived. The proposed modulation technique for the three-level NPC VSI includes the maximum and minimum of the three-phase sinusoidal reference voltages with zero-sequence voltage injection concept. The proposed modified CB-PWM strategy incorporates a novel method that requires only of one triangular carrier wave for generate the gating pulses in three-level NPC VSI. It has the advantages of being simplifying the algorithm with no need of complex two/multi-carrier pulsewidth modulation or space vector modulation (SVM) and it's also simple to implement. The possibility of the proposed CB-PWM technique has been verified though computer simulation and experimental results.

• Journal of information and communication convergence engineering
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• 제11권4호
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• pp.288-292
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• 2013

In this paper, a carbon implant is investigated in detail from the perspectives of performance advantages and side effects for the thick n-type metal-oxide-semiconductor field-effect transistor (n-MOSFET). Threshold voltage ($V_{th}$) adjustment using a carbon implant significantly improves the $V_{th}$ mismatch performance in a thick (3.3-V) n-MOS transistor. It has been reported that a bad mismatch occurs particularly in the case of 0.11-${\mu}m$ $V_{th}$ node technology. This paper investigates a carbon implant process as a promising candidate for the optimal $V_{th}$ roll-off curve. The carbon implant makes the $V_{th}$ roll-off curve perfectly flat, which is explained in detail. Further, the mechanism of hot carrier injection lifetime degradation by the carbon implant is investigated, and new process integration involving the addition of a nitrogen implant in the lightly doped drain process is offered as its solution. This paper presents the critical side effects, such as Isub increases and device performance shifts caused by the carbon implant and suggests an efficient method to avoid these issues.

• 한국자기학회:학술대회 개요집
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• 한국자기학회 2003년도 하계학술연구발표회 및 한.일 공동심포지엄
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• pp.66-67
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• 2003

Bismuth (Bi) has been an attractive materials for studying spin dependent transport properties because it shows very large magnetoresistance (MR) resulting from its highly anisotropic Fermi surface, low carrier concentrations, long carrier mean free path 1 and small effective carrier mass m*[1-3]. With all the intriguing properties, difficulty in fabrication of high quality Bi thin films may have prevented extensive application of Bi in magnetic field sensing and spin-injection devices. Previous works found that the surface roughness and small grain size in 100-200 nm of Bi thin film made by evaporation and sputtering are major causes of low MR. Although relatively higher MR in electrodeposited Bi followed by annealing was reported, it still suffers from rough sulfate roughness which is so severs that it is hardly able to make a field sensing and spin-injection device using conventional photolithography process.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권2호
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• pp.191-197
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• 2016

In this paper, we investigated the hotcarrier injection (HCI) mechanism, one of the most important reliability issues, in 10 nm node Input/Output (I/O) bulk FinFET. The FinFET has much intensive HCI damage in Fin-bottom region, while the HCI damage for planar device has relatively uniform behavior. The local damage behavior in the FinFET is due to the geometrical characteristics. Also, the HCI is significantly affected by doping profile, which could change the worst HCI bias condition. This work suggested comprehensive understanding of HCI mechanisms and the guideline of doping profile in 10 nm node I/O bulk FinFET.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2016년도 제50회 동계 정기학술대회 초록집
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• pp.230.1-230.1
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• 2016

본 연구에서는 Host-Dopant system 기반 적색 인광 OLED의 Emitting layer(EML)에서 doping 위치에 따른 특성 변화를 분석하였다. EML은 host 물질로 60 nm 두께의 CBP를 사용하고, 적색 발광을 위해 10 %의 $Ir(btp)_2$를 CBP의 Front, Middle, Back side에 각각 20 nm씩 doping하였다. 본 구조의 적색 인광 OLED는 current density, luminance, efficiency, EL spectrum 등을 통해 전기적, 광학적 특성 변화를 확인하였다. Front, Back side에 doping으로 인한 CBP의 Energy level이 3.6 eV에서 1.9 eV로 감소하여 각각 HTL/EML, EML/HBL의 경계에 carrier direct injection이 활성화 되었고, 이로 인한 charge balance의 저하를 확인하였다. EL spectrum결과 각 소자는 CBP의 618 nm 파장 외에도, 추가적으로 TPBi의 398 nm, NPB의 456 nm의 파장을 보였다. 이를 통해 doping 위치에 따라 exciton이 형성되는 recombination zone이 이동하고 있음을 확인하였고, Front side는 6 V의 인가전압에서는 발광 파장이 398 nm에서 높은 값을 보이나 8 V, 10 V, 12 V에서 618 nm에서 높은 값을 보이는 것으로 인가전압에 의해 recombination zone이 HTL쪽으로 이동되는 것 또한 확인하였다.

• 대한전기학회논문지
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• 제35권10호
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• pp.465-472
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• 1986

The present study was carried out to investigate the mechanism which control the voltage instability and the breakdown of CVD Al2O3 on Si substrates. Our sample were metal-Al2O3-Oi Capacitors with both Al and Au field plates. Electron injection and trapping, with resultant positive flatband voltage shift, occur at fields as low as 1-2[MV/cm.] We developed an approximate method for computing the location of the centroid of the trapped electrons. Our results indicate that the electrons are trapped near the injecting interface, at least for fields less than about 5[MV/cm ] Because of continued charging, a true steady state is probably never reached, and the only unique I-V curve is the one obtained initially, when the traps are empty. We measured this I-V curve for both polarities of applied voltage, using a fresh sample for each point. The observed current densities are much larger than those obtained in thermally grawn SiO2.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2013년도 제44회 동계 정기학술대회 초록집
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• pp.266-266
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• 2013

We show a set-up of poly (4,4'-aminotriphenylene hexafluoroisopropylidenediphthalimide) (6F-TPA PI)/Al sample in which holes are injected by photoelectron emission process instead of direct charge carrier injection via metal electrode. In this process, an irreversible electrical phase transition of 6F-TPA PI is found in contrast to the Al/6F-TPA PI/Al structure, leading to a write-once-readmany behavior. The photoelectron spectroscopy results measured before and after the switching process revealed that the irreversible electrical phase transition of 6F-TPA PI is attributed to the chemical modification of the carbonyl group in phthalimide moiety.

• 전자공학회논문지A
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• 제30A권2호
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• pp.36-45
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• 1993

The n-channel MOSFETs with gate-$n^{-}$S/D overlapped structure have been fabricated by ITLDD(inverse-T gate lightly doped drain) technology. The gate length(L$_{mask}$) was 0.8$\mu$m. The degradation effects of hot carriers injected into the gate oxide were analyzed in terms of threshold voltage, transconductance and drain current variations. The degradation dependences on the gate voltage and drain voltage were characterized. The devices with higher n-concentration showed higher resistivity against the hot carrier injection. As the results of investigating the lifetime of the device, the lifetime showed longer than 10 years at V$_{d}$ = 5V for the overlapped devices with the implantation of an phosphorus dose of 5$\times$10$^{13}$ cm$^{-2}$ and an energy of 80 keV in the n$^{-}$resion.

• JSTS:Journal of Semiconductor Technology and Science
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• 제2권3호
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• pp.157-163
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• 2002

A new flash EEPROM device with p^＋ poly-Si control gate and n^＋ poly-Si floating side gate was fabricated and characterized. The n^＋ poly-Si gate is formed on both sides of the p^＋ poly-Si gate, and controls the underneath channel conductivity depending on the number of electron in it. The cell was programmed by hot-carrier-injection at the drain extension, and erased by direct tunneling. The proposed EEPROM cell can be scaled down to 50 nm or less. Shown were measured programming and erasing characteristics. The channel resistance with the write operation was increased by at least 3 times.