• 제목/요약/키워드: capacitance - voltage (C-V)

검색결과 321건 처리시간 0.023초

용량성 압력센서의 집적화에 관한 연구 (Study on Integrated for Capacitive Pressure Sensor)

  • 이윤희
    • 전자공학회논문지T
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    • 제35T권1호
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    • pp.48-58
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    • 1998
  • 본 논문은 센서에서 수반되는 기생용량과 온도 드리프트 및 누설전류의 영향을 경감하기 위한 C-V변환회로 및 C-V변환회로에 관한 실험결과를 제시하고, 또한 논문에서 제안한 센싱 주파수를 기준주파수로 나누어줌으로써 상기 영향들을 줄일 수 있는 새로운 인터페이스 회로를 제시한다 이 회로는 용량비의 출력신호를 디지털 방식으로 16진수로 계수 함으로써 신호의 전송이나 컴퓨터 처리가 쉬울 뿐 아니라 비트수의 증가에 따라 분해 능을 향상시킬 수 있는 이점도 있다. 시작한 인터페이스 회로의 C-V 및 C-F 변환회로에서 전원전압 4.0V, 피이드백 커패시턴스10pF, 압력 0∼10 KPa범위에서 감도는 각각 28 ㎷/㎪·V, -6.6 ㎐/㎩로서 양호하였고, 온도 드리프트 특성은 0.051 %F.S./℃ 및 0.078 %F.S./℃로서 크게 개선되었다.

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The Effect of Anodizing on the Electrical Properties of ZrO2 Coated Al Foil for High Voltage Capacitor

  • Chen, Fei;Park, Sang-Shik
    • Applied Science and Convergence Technology
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    • 제24권2호
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    • pp.33-40
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    • 2015
  • $ZrO_2$ and Al-Zr composite oxide film was prepared by vacuum assisted sol-gel dip coating method and anodizing. $ZrO_2$ films annealed above $400^{\circ}C$ have tetragonal structure. $ZrO_2$ layers inside etch pits were successfully coated from the $ZrO_2$ sol. The double layer structures of samples were obtained after being anodized at 100 V to 600 V. From the TEM images, it was found that the outer layer was $Al_2O_3$, the inner layer was multi-layer of $ZrO_2$, Al-Zr composite oxide and Al hydrate. The capacitance of $ZrO_2$ coated foil exhibited about 28.3% higher than that of non-coating foil after being anodized at 100 V. The high capacitance of $ZrO_2$ coated foils anodized at 100 V can be attributed to the relatively high percentage of inner layer in total thickness. The electrical properties, such as withstanding voltage and leakage current of coated and non-coated Al foils showed similar values. From the results, $ZrO_2$ and Al-Zr composite oxide is promising to be used as the partial dielectric of high voltage capacitor to increase the capacitance.

Pt/$LiNbO_3$/AIN/Si(100) 구조의 전기적 특성 (Electrical Properties of Pt/$LiNbO_3$/AIN/Si(100) structures)

  • 정순원;정상현;인용일;김광호
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2001년도 하계학술대회 논문집
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    • pp.58-61
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    • 2001
  • Metal-insulator-semiconductor (MIS) C-V properties with high dielectric AIN thin films showed no hysteresis and good interface properties. The dielectric constant of the AIN film calculated from the capacitance at the accumulation region in the capacitance-voltage(C-V) characteristics was about 8. The C-V characteristics of MFIS capacitor showed a hysteresis loop due to the ferroelectric nature of the LiNbO$_3$ thin films. Typical dielectric constant value of LiNbO$_3$ film of MFIS device was about 23. The memory window width was about 1.2V at the gate voltage of $\pm$5 V ranges. Typical gate leakage current density of the MFIS structure was the order of 10$^{-9}$ A/cm$^2$ at the range of within $\pm$500 kV/cm. The ferroelectric capacitors showed no polarization degradation up to about 10$^{11}$ switching cycles when subjected to symmetric bipolar voltage pulse(peak-to-peak 8V, 50% duty cycle) in the 500kHz.

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Capacitance - Voltage 방법을 이용한 MOSFET의 유효 채널 길이 추출 (Extracting the Effective Channel Length of MOSFET by Capacitance - Voltage Method.)

  • 김용구;지희환;박성형;이희덕
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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    • pp.679-682
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    • 2003
  • Improvement in MOS fabrication technology have led to high-density high-performance integrated circuits with MOSFET channel lengths in the sub-micron range. For devices of the size, transistor characteristics become highly sensitive to effective channel length. We propose a new approach to extract the effective channel length of MOSFET by Capacitance-Voltage (C-V) method. Gate-to-Source, Drain capacitance ( $C_{gsd}$) are measured and the effective channel length can be extracted. In addition, compared to l/$\beta$ method and Terada method, which has been point out that it fails to extract the accurate effective channel length of the devices, we prove that our approach still works well for the devices with down to sub-micron regime.e.

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펄스형 고전압 측정용 용량성 분압기 (Capacitive Voltage Divide for a Pulsed High-Voltage Measurement)

  • 장성덕;손윤규;권세진;오종석;조무현
    • 대한전기학회논문지:전기물성ㆍ응용부문C
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    • 제54권2호
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    • pp.63-68
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    • 2005
  • Total 12 units of high power klystron-modulator systems as microwave source are under operation for 2.5 GeV electron linear accelerator in Pohang Light Source (PLS) linac. The klystron-modulator system has an important role for the stable operation to improve an availability statistics of overall system performance of klystron-modulator system. RF power and beam power of klystron are precisely measured for the effective control of electron beam. A precise measurement and measurement equipment with good response characteristics are demanded for this. Input power of klystron is calculated from the applied voltage and the current on its cathode. Tiny measurement error severely effects RF output power value of klystron. Therefore, special care is needed to measure precise beam voltage. Capacitive voltage divider (CVD), which divides input voltage as capacitance ratio, is intended for the measurement of a beam voltage of 400 kV generated from the klystron-modulator system. Main parameter to determine standard capacitance in the high arm of CVD is dielectric constant of insulation oil. Therefore CVD should be designed to have a minimum capacitance variation due to voltage, frequency and temperature in the measurement range. This paper will be present and discuss the design concept and analysis of capacitive voltage divider for a pulsed high-voltage measurement, and the empirical relations between capacitance effects and oil temperature variation.

AIN 버퍼층을 사용한 MFIS 구조의 제작 및 특성 (Fabrications and properties of MFIS structure using AIN buffer layer)

  • 정순원;김용성;이남열;김진규;정상현;김광호;유병곤;이원재;유인규
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2000년도 추계종합학술대회 논문집(2)
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    • pp.29-32
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    • 2000
  • Meta1-ferroelectric-insulator-semiconductor(MFIS) devices using Pt/LiNbO$_{3}$/AIN/Si structure were successfully fabricated. AIN thin films were made into metal-insulator-semiconductor(MIS) devices by evaporating aluminum in a dot array on the film surface. The dielectric constant of the AIN film calculated from the capacitance in the accumulation region in the capacitance-voltage(C-V ) characteristic is 8. The gate leakage current density of MIS devices using a aluminum electrode showed the least value of 1$\times$10$^{-8A}$ $\textrm{cm}^2$ order at the electric field of 500㎸/cm. A typica] value of the dielectric constant of MFIS device was about 23 derived from 1MHz capacitance-voltage (C-V) measurement and the resistivity of the film at the field of 500㎸/cm was about 5.6$\times$ 10$^{13}$ $\Omega$.cmcm

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SiO$_2$/Si$_3$N$_4$ 이중 박막의 C-V 특성 (Capacitance-Voltage Characteristics in the Double Layers of SiO$_2$/Si$_3$N$_4$)

  • Hong, Nung-Pyo;Hong, Jin-Woong
    • 대한전기학회논문지:전기물성ㆍ응용부문C
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    • 제52권10호
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    • pp.464-468
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    • 2003
  • The double layers of $SiO_2$/$Si_3$$N_4$ have superior charge storage stability than a single layer of $SiO_2$. Many researchers are very interested in the charge storage mechanism of $SiO_2$/$Si_3$$N_4$ [1,2]. In this paper, the electrical characteristics of thermal oxide and atmospheric pressure chemical vapor deposition (APCVD) of $Si_4$$N_4$ have been investigated and explained using high frequency capacitance-voltage measurements. Additionally, this paper will describe capacitance-voltage characteristics for double layers of $SiO_2$/$Si_4$$N_4$ by "Athena", a semiconductor device simulation tool created by Silvaco, Inc.vaco, Inc.

열처리 온도에 따른 Sr계 박막의 표면 및 전기적인 특성 (Surface and Electrical Properties of Sr Based Thin Film with Annealing Temperature)

  • 최운식;조춘남;김진사
    • 한국전기전자재료학회논문지
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    • 제27권2호
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    • pp.132-135
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    • 2014
  • The Sr based ceramic thin films were deposited on Si substrate by RF magnetron sputtering method. And Sr based thin films were annealed at $500{\sim}700^{\circ}C$ using RTA. The surface roughness showed about 2.4 nm in annealed thin film at $600^{\circ}C$. The capacitance density of Sr based thin films were increased with the increase of annealing temperature. The maximum capacitance density of $0.6{\mu}F/cm^2$ was obtained by annealing temperature at $700^{\circ}C$. The voltage dependence of dielectric loss showed about 0.02 in voltage ranges of -10~+10 V. The leakage current density of annealing temperature of $600^{\circ}C$ was the $4.0{\times}10^{-6}\;A/cm^2$ at applied voltage of -5~+5 V.

A Study of the Relationship Analysis of Power Conversion and Changed Capacitance in the Depletion Region of Silicon Solar Cell

  • Kim, Do-Kyeong;Oh, Yeong-Jun;Kim, Sang-Hyun;Hong, Kyeong-Jin;Jung, Haeng-Yeon;Kim, Hoy-Jin;Jeon, Myeong-Seok
    • Transactions on Electrical and Electronic Materials
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    • 제14권4호
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    • pp.177-181
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    • 2013
  • In this paper, silicon solar cells are analyzed regarding power conversion efficiency by changed capacitance in the depletion region. For the capacitance control in the depletion region of silicon solar cell was applied for 10, 20, 40, 80, 160 and 320 Hz frequency band character and alternating current(AC) voltage with square wave of 0.2~1.4 V. Academically, symmetry formation of positive and negative change of the p-n junction is similar to the physical effect of capacitance. According to the experiment result, because input of square wave with alternating current(AC) voltage could be observed to changed capacitance effect by indirectly method through non-linear power conversion (Voltage-Current) output. In addition, when input alternating current(AC) voltage in the silicon solar cell, changed capacitance of depletion region with the forward bias condition and reverse bias condition gave a direct effect to the charge mobility.

Electrical Characteristics of Thin SiO$_2$Layer

  • Hong, Nung-Pyo;Hong, Jin-Woong
    • KIEE International Transactions on Electrophysics and Applications
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    • 제3C권2호
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    • pp.55-58
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    • 2003
  • This paper examines the electrical characteristic of single oxide layer due to various diffusion conditions, substrate orientations, substrate resistivity and gas atmosphere in a diffusion furnace. The oxide quality was examined through the capacitance-voltage characteristic due to the annealing time after oxidation process, and the capacitance-voltage characteristics of the single oxide layer by will be described via semiconductor device simulation.