• 한국전기전자재료학회논문지
• /
• 제20권2호
• /
• pp.118-123
• /
• 2007

The purpose of this work was to investigate the design and fabrication process effects on electrical properties in high capacitance multilayer ceramic capacitor (MLCC) with nickel electrode. Dielectric breakdown voltage and insulation resistance value were decreased with increasing stack layer number, but dielectric constant and capacitance were increased. With increasing green sheet thickness, dielectric breakdown voltage, C-V and I-V properties were also increased. The major reasons of the effects were thought to be the defects generated extrinsically during fabrication process and interfacial reactions formed between nickel electrode and dielectric layer. These investigations clearly showed the influence of both green sheet thick ness and stack layer number on the electrical properties in fabricating the MLCC.

• 한국진공학회지
• /
• 제5권4호
• /
• pp.333-340
• /
• 1996

Cu 확산방지막으로서의 Tin의 특성을 면저항 특정, X선 회절 분석, SEM, AES, capacitance-voltage(C-V) 측정에 의하여 평가하고, Cu의 확산을 민감하게 알아내는 정도를 특성 평가 방법간에 비교하였다. 여러 가지 증착방법에 의하여 Cu/TiN/Ti/SiO2/Si 구조의 다층 박막시편을 제작하였으며, 이 시편을 10% H2/90% Ar분위기, 열처리 온도 500~$800{\circ}C$ 범위에서 2시간 동안 열처리하였다. TiN의 Cu 확산방지 효과가 소멸된 경우 Cu 박막 표면에서 불규칙한 모양의 spot을 관찰할 수 있었으며 outdiffusion된 Si를 검출할 수 있었다. MOS capacitor의 C-V 특성은 열처리 온도에 따라 급격하게 변화하였다. C-V 측정에서 inversion capacitance는 열처리 온도 500~$700^{\circ}C$범위에서 열처리 온도가 높아질수록 감소하다가 $800^{\circ}C$에서 크게 증가하였으며, 이러한 특성의 변화는 TiN을 통해서 $SiO_2$와 Si내로 확산된 Cu에 의하여 발생되는 것으로 생각된다.

• 한국전기전자재료학회논문지
• /
• 제21권8호
• /
• pp.699-705
• /
• 2008

Capacitance versus voltage (C-V) characteristics of Ge-nanocrystal (NC)-embedded metal-oxide-semiconductor (MOS) capacitors with $HfO_2$ gate material were investigated in this work. The current versus voltage (I-V) curves obtained from Ge-NC-embedded MOS capacitors fabricated with the $NH_3$ annealed $HfO_2$ gate material reveal the reduction of leakage current, compared with those of MOS capacitors fabricated with the $O_2$ annealed $HfO_2$ gate material. The C-V curves of the Ge-NC-embedded MOS capacitor with $HfO_2$ gate material annealed in $NH_3$ ambient exhibit counterclockwise hysteresis loop of about 3.45 V memory window when bias voltage was varied from -10 to + 10 V. The observed hysteresis loop indicates the presence of charge storages in the Ge NCs caused by the Fowler-Nordheim (F-N) tunneling. In addition, capacitance versus time characteristics of Ge-NC-embedded MOS capacitors with $HfO_2$ gate material were analyzed to investigate their retention property.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2015년도 제46회 하계학술대회
• /
• pp.1140-1140
• /
• 2015

In this paper, the MIM thin films were deposited on Si substrate by sputtering method. And MIM thin films were annealed at $400{\sim}600^{\circ}C$ using RTA. The capacitance density of MIM thin films were increased with the increase of annealing temperature. The maximum capacitance density of $0.62{\mu}F/cm^2$ was obtained by annealing temperature at $600^{\circ}C$. The voltage dependence of dielectric loss showed about 0.03 in voltage ranges of -10~+10 V.

• 전기전자학회논문지
• /
• 제10권2호통권19호
• /
• pp.156-160
• /
• 2006

Al2O3 층의 유무에 따른 Ge 나노입자가 형성된 MOS 구조의 캐패시터의 전압에 대한 캐패시턴스 (C-V)의 특성을 측정하였다. Al20O층이 형성된 MOS 캐패시터의 C-V 곡선은 전압의 변화에 대해 나타나는 반시계 방항의 히스테리시스 특성은 Si 기판과 Ge 나노입자 사이를 전자가 터널링하여 Ge 나노입자에 저장되었기 때문이다. Al2O3 층이 없는 MOS 캐패시터의 경우, 시계 방향의 히스테리시스 특성과 좌측으로 이동한 플랫-밴드 전압 값을 볼 수 있다. 이것은 SiO2 층에 존재하는 산소 결원 (oxygen vacancy) 으로 인한 전하 트랩이 이러한 특성을 나타냈다 할 수 있다. 또, 백색광이 C-V 특성에 미치는 영향에 대하여 논하였다.

• 한국전기전자재료학회논문지
• /
• 제20권1호
• /
• pp.47-52
• /
• 2007

Organic field-effect transistors (OFETS) are of interest for use in widely area electronic applications. We fabricated a copper phthalocyanine (CuPc) based field-effect transistor with varying channel length. The CuPc FET device was made a top-contact type and the channel length was a $100\;{\mu}m,\;50\;{\mu}m,\;40\;{\mu}m,\;and\;30\;{\mu}m$ and the channel width was a fixed at 3 mm. We observed a typical current-voltage (I-V) characteristics in CuPc FET with varying channel length (L) and we calculated the effective mobility. Also, we measured a capacitance-voltage (C-V) by applied bias voltage with varying frequency at 43, 100, 1000 Hz.

• 한국재료학회지
• /
• 제5권8호
• /
• pp.1020-1025
• /
• 1995

Au/Si(100) Schotty diode를 l00k~300k 온도범위에서 current voltage(I-V), capacitance-voltage(C-V)측정을 하였다. 얻어진 Schottky barrier height(SBH)갑은 실온에서 두측정값 모두 (0.79$\pm$0.02)eV 이다. 그러나 온도가 감소할수록 I-V측정에서 SBH는 선형적으로 감소하고 C-V측정에서 SBH는 온도에 따른 변화가 관찰되지 않았다. 이것은 낮은 온도에서 열이온 방출 이론을 따르지 않는다는 것을 나타낸다. 이것으로 재결합 전류를 고려하여 계산해 본 결과 I-V에서도 SBH의 변화가 관찰되지 않으므로 C-V측정과 일치됨을 보았다. 이런 상반된 결과를 가져오는 이유는 전류수송현상이 온도에 따라 변화하므로 생긴 것임을 알 수 있었다.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2001년도 추계학술대회 논문집 Vol.14 No.1
• /
• pp.34-37
• /
• 2001

In this study, the capacitance-voltage properties of $(Sr_{1-x}\cdot Ca_x)TiO_3(0.05{\leq}x{\leq}0.20)$-based grain boundary layer ceramics were investigated. The ceramics were fabricated by the conventional mixed oxide method. The sintering temperature and time were $1480\sim1500^{\circ}C$ and 4 hours. respectively. The 2nd phase formed by the thermal diffusion of CuO from the surface leads to very excellent dielectric properties, that is, ${\varepsilon}_r$ >50000, tan$\delta$ <0.05, ${\Delta}C$ < ${\pm}10%.$ The capacitance is almost unchanged below about 20[V] but it decreases slowly about 20[V]. The results of the capacitance-voltage properties indicated that the grain boundary was composed of the continuous insulating layers.

• Journal of Electrical Engineering and Technology
• /
• 제11권6호
• /
• pp.1656-1663
• /
• 2016

A capacitive wireless power transfer (C-WPT) system uses an electric field to transmit power through a physical isolation barrier which forms a pair of ac link capacitors between the metal plates. However, the physical dimension and low dielectric constant of the interface medium severely limit the effective link capacitance to a level comparable to the main switch output capacitance of the transmitting circuit, which thus narrows the soft-switching range in the light load condition. Moreover, by fundamental limit analysis, it can be proved that such a low link capacitance increases operating frequency and capacitor voltage stress in the full load condition. In order to handle these problems, this paper investigates optimal design of double matching transformer networks for C-WPT. Using mathematical analysis with fundamental harmonic approximation, a design guideline is presented to avoid unnecessarily high frequency operation, to suppress the voltage stress on the link capacitors, and to achieve wide ZVS range even with low link capacitance. Simulation and hardware implementation are performed on a 5-W prototype system equipped with a 256-pF link capacitance and a 200-pF switch output capacitance. Results show that the proposed scheme ensures zero-voltage-switching from full load to 10% load, and the switching frequency and the link capacitor voltage stress are kept below 250 kHz and 452 V, respectively, in the full load condition.

• KIEE International Transactions on Electrophysics and Applications
• /
• 제11C권4호
• /
• pp.142-145
• /
• 2001

The residual DC phenomena in the in-plane switching(IPS)-liquid crystal display(LCD) by the voltage-transmittance (V-T) and capacitance-voltage (C-V) hysteresis method on rubbed polyimide (PI) surfaces were studied. We found that the residual DC voltage in the IPS-LCD was decreasing with the increasing concentration of cyano LCs. The residual DC voltage of the IPS-LCD can be improved by the high polarity of cyano LCs.