• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.20 no.2
• /
• pp.118-123
• /
• 2007

The purpose of this work was to investigate the design and fabrication process effects on electrical properties in high capacitance multilayer ceramic capacitor (MLCC) with nickel electrode. Dielectric breakdown voltage and insulation resistance value were decreased with increasing stack layer number, but dielectric constant and capacitance were increased. With increasing green sheet thickness, dielectric breakdown voltage, C-V and I-V properties were also increased. The major reasons of the effects were thought to be the defects generated extrinsically during fabrication process and interfacial reactions formed between nickel electrode and dielectric layer. These investigations clearly showed the influence of both green sheet thick ness and stack layer number on the electrical properties in fabricating the MLCC.

• Journal of the Korean Vacuum Society
• /
• v.5 no.4
• /
• pp.333-340
• /
• 1996

The properties of TiN as a barrier against Cu diffusion ere studied by sheet resistance measurement, X-ray diffraction, scanning electron microscopy, Auger electron spectroscopy, and capacitance-voltage(C-V) measurement. The sensitivities of the various methods were compared. Specimens with Cu/TiN/Ti/SiO2/Si structure were prepared by various deposition techniques and annealed at various temperatures ranging from $500^{\circ}C$ to $800^{\circ}C$ in 10%H2/90%Ar ambient for hours. As the effectiveness of the barrier property of TiN against Cu diffusion was vanished, the irregular-shaped sports were observed and outdiffused Si were detected on the surface of the Cu thin film. The C-V characteristics of the MOS capacitors varied drastically with annealing temperatures. In C-V measurement, the inversion capacitance decreased at annealing temperature range from $500^{\circ}C$ to $700^{\circ}C$ and increased remarkably at $800^{\circ}C$. These variations may be due to the Cu diffusion through TiN into $SiO_2$ and Si.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.21 no.8
• /
• pp.699-705
• /
• 2008

Capacitance versus voltage (C-V) characteristics of Ge-nanocrystal (NC)-embedded metal-oxide-semiconductor (MOS) capacitors with $HfO_2$ gate material were investigated in this work. The current versus voltage (I-V) curves obtained from Ge-NC-embedded MOS capacitors fabricated with the $NH_3$ annealed $HfO_2$ gate material reveal the reduction of leakage current, compared with those of MOS capacitors fabricated with the $O_2$ annealed $HfO_2$ gate material. The C-V curves of the Ge-NC-embedded MOS capacitor with $HfO_2$ gate material annealed in $NH_3$ ambient exhibit counterclockwise hysteresis loop of about 3.45 V memory window when bias voltage was varied from -10 to + 10 V. The observed hysteresis loop indicates the presence of charge storages in the Ge NCs caused by the Fowler-Nordheim (F-N) tunneling. In addition, capacitance versus time characteristics of Ge-NC-embedded MOS capacitors with $HfO_2$ gate material were analyzed to investigate their retention property.

• Proceedings of the KIEE Conference
• /
• 2015.07a
• /
• pp.1140-1140
• /
• 2015

In this paper, the MIM thin films were deposited on Si substrate by sputtering method. And MIM thin films were annealed at $400{\sim}600^{\circ}C$ using RTA. The capacitance density of MIM thin films were increased with the increase of annealing temperature. The maximum capacitance density of $0.62{\mu}F/cm^2$ was obtained by annealing temperature at $600^{\circ}C$. The voltage dependence of dielectric loss showed about 0.03 in voltage ranges of -10~+10 V.

• Journal of IKEEE
• /
• v.10 no.2 s.19
• /
• pp.156-160
• /
• 2006

Capacitance versus voltage (C-V) curves of Ge-nanocrystal (NC)-embedded MOS capacitors with and without a single capping Al2O3 layer are characterized in this work. C-V curves of the Ge-NC-embedded MOS capacitor with the A12O3 layer are counterclockwise in the voltage sweeps, which indicates tile presence of charge storages in the Ge NCs by the tunnelling of charge carriers between the Si substrate and the Ge NCs. In the Ge-NC-embedded MOS capacitor without Al2O3 layer, clockwise hysteresis of the C-V curves and leftward shifts of the flat band voltages are observed for the embedded MOS capacitor without the Al2O3 layer. It is suggested that the characteristics of the C-V curves are due to the charge trapping at oxygen vacancies within a SiO2 layer. In addition, the illumination of the white light enhances the lower capacitance part of the C-V hysteresis. The origin for the enhancement is discussed in this paper.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.20 no.1
• /
• pp.47-52
• /
• 2007

Organic field-effect transistors (OFETS) are of interest for use in widely area electronic applications. We fabricated a copper phthalocyanine (CuPc) based field-effect transistor with varying channel length. The CuPc FET device was made a top-contact type and the channel length was a $100\;{\mu}m,\;50\;{\mu}m,\;40\;{\mu}m,\;and\;30\;{\mu}m$ and the channel width was a fixed at 3 mm. We observed a typical current-voltage (I-V) characteristics in CuPc FET with varying channel length (L) and we calculated the effective mobility. Also, we measured a capacitance-voltage (C-V) by applied bias voltage with varying frequency at 43, 100, 1000 Hz.

• Korean Journal of Materials Research
• /
• v.5 no.8
• /
• pp.1020-1025
• /
• 1995

The Schottky barrier hieght(SBH) of Au/n-Si(100) were investigated by current-voltage(I-V) and capacitance voltage(C-V) measurement within a temperature range of l00K∼300K. The values of SBH at room temperature obtained from these two measurements were (0.79${\pm}$0.02)eV. The SBH obtained from the C-V measurement was temperature independent, while that obtained from the I-V measurement decreased linearly with decreasing temperature. This indicates that the Schottky diode has deviated from the thermionic emission theory at low-temperature, Thus, other current transport processes were considered and the contribution of recombination current was dominant at low temperature. We found that it leads to a lower SBH value. Thus, the conflicating results between C-V and I-V measurement were explained, C-V measurement is believed to yield mare reliable SBH values in present study since it is not affected by the current transport uncertainties.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2001.11b
• /
• pp.34-37
• /
• 2001

In this study, the capacitance-voltage properties of $(Sr_{1-x}\cdot Ca_x)TiO_3(0.05{\leq}x{\leq}0.20)$-based grain boundary layer ceramics were investigated. The ceramics were fabricated by the conventional mixed oxide method. The sintering temperature and time were $1480\sim1500^{\circ}C$ and 4 hours. respectively. The 2nd phase formed by the thermal diffusion of CuO from the surface leads to very excellent dielectric properties, that is, ${\varepsilon}_r$ >50000, tan$\delta$ <0.05, ${\Delta}C$ < ${\pm}10%.$ The capacitance is almost unchanged below about 20[V] but it decreases slowly about 20[V]. The results of the capacitance-voltage properties indicated that the grain boundary was composed of the continuous insulating layers.

• Journal of Electrical Engineering and Technology
• /
• v.11 no.6
• /
• pp.1656-1663
• /
• 2016

A capacitive wireless power transfer (C-WPT) system uses an electric field to transmit power through a physical isolation barrier which forms a pair of ac link capacitors between the metal plates. However, the physical dimension and low dielectric constant of the interface medium severely limit the effective link capacitance to a level comparable to the main switch output capacitance of the transmitting circuit, which thus narrows the soft-switching range in the light load condition. Moreover, by fundamental limit analysis, it can be proved that such a low link capacitance increases operating frequency and capacitor voltage stress in the full load condition. In order to handle these problems, this paper investigates optimal design of double matching transformer networks for C-WPT. Using mathematical analysis with fundamental harmonic approximation, a design guideline is presented to avoid unnecessarily high frequency operation, to suppress the voltage stress on the link capacitors, and to achieve wide ZVS range even with low link capacitance. Simulation and hardware implementation are performed on a 5-W prototype system equipped with a 256-pF link capacitance and a 200-pF switch output capacitance. Results show that the proposed scheme ensures zero-voltage-switching from full load to 10% load, and the switching frequency and the link capacitor voltage stress are kept below 250 kHz and 452 V, respectively, in the full load condition.

• KIEE International Transactions on Electrophysics and Applications
• /
• v.11C no.4
• /
• pp.142-145
• /
• 2001

The residual DC phenomena in the in-plane switching(IPS)-liquid crystal display(LCD) by the voltage-transmittance (V-T) and capacitance-voltage (C-V) hysteresis method on rubbed polyimide (PI) surfaces were studied. We found that the residual DC voltage in the IPS-LCD was decreasing with the increasing concentration of cyano LCs. The residual DC voltage of the IPS-LCD can be improved by the high polarity of cyano LCs.