• Title/Summary/Keyword: bump

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A Study of the fracture of intermetallic layer in electroless Ni/Au plating (무전해 니켈/금도금에서의 내부 금속층의 결함에 대한 연구)

  • 박수길;정승준;김재용;엄명헌;엄재석;전세호
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 1999.05a
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    • pp.708-711
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    • 1999
  • The Cu/Ni/Au lamellar structure is extensively used as an under bump metallization on silicon file, and on printed circuit board(PCB) pads. Ni is plated Cu by either electroless Ni plating, or electrolytic Ni plating. Unlike the electrolytic Ni plating, the electroless Ni plating does not deposit pure Ni, but a mixture of Ni and phosphorous, because hypophosphite Is used in the chemical reaction for reducing Ni ions. The fracture crack extended at the interface between solder balls of plastic ball grid (PBGA) package and conducting pads of PCB. The fracture is duets to segregation at the interface between Ni$_3$Sn$_4$intermetallic and Ni-P layer. The XPS diffraction results of Cu/Ni/Au results of CU/Ni/AU finishs showed that the Ni was amorphous with supersaturated P. The XPS and EDXA results of the fracture surface indicated that both of the fracture occurred on the transition lesion where Sn, P and Ni concentrations changed.

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HV-SoP Technology for Maskless Fine-Pitch Bumping Process

  • Son, Jihye;Eom, Yong-Sung;Choi, Kwang-Seong;Lee, Haksun;Bae, Hyun-Cheol;Lee, Jin-Ho
    • ETRI Journal
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    • v.37 no.3
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    • pp.523-532
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    • 2015
  • Recently, we have witnessed the gradual miniaturization of electronic devices. In miniaturized devices, flip-chip bonding has become a necessity over other bonding methods. For the electrical connections in miniaturized devices, fine-pitch solder bumping has been widely studied. In this study, high-volume solder-on-pad (HV-SoP) technology was developed using a novel maskless printing method. For the new SoP process, we used a special material called a solder bump maker (SBM). Using an SBM, which consists of resin and solder powder, uniform bumps can easily be made without a mask. To optimize the height of solder bumps, various conditions such as the mask design, oxygen concentration, and processing method are controlled. In this study, a double printing method, which is a modification of a general single printing method, is suggested. The average, maximum, and minimum obtained heights of solder bumps are $28.3{\mu}m$, $31.7{\mu}m$, and $26.3{\mu}m$, respectively. It is expected that the HV-SoP process will reduce the costs for solder bumping and will be used for electrical interconnections in fine-pitch flip-chip bonding.

Flip Chip Assembly on PCB Substrates with Coined Solder Bumps (코인된 솔더 범프를 형성시킨 PCB 기판을 이용한 플립 칩 접속)

  • 나재웅;백경욱
    • Proceedings of the International Microelectronics And Packaging Society Conference
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    • 2002.11a
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    • pp.21-26
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    • 2002
  • Solder flip chip bumping and subsequent coining processes on PCB were investigated to solve the warpage problem of organic substrates for high pin count flip chip assembly by providing good co-planarity. Coining of solder bumps on PCB has been successfully demonstrated using a modified tension/compression tester with height, coining rate and coining temperature variables. It was observed that applied loads as a function of coined height showed three stages as coining deformation : (1) elastic deformation at early stage, (2) linear increase of applied load, and (3) rapid increase of applied load. In order to reduce applied loads for coining solder bumps on PCB, effects of coining process parameters were investigated. Coining loads for solder bump deformation strongly depended on coining rates and coining temperatures. As coining rates decreased and process temperature increased, coining loads decreased. Among the effect of two factors on coining loads, it was found that process temperature had more significant effect to reduce applied coining loads during the coining process. Lower coining loads were needed to prevent substrate damages such as micro-via failure and build-up dielectric layer thickness change during applying loads. For flip chip assembly, 97Pb/Sn flip chip bumped devices were successfully assembled on organic substrates with 37Pb/Sn coined flip chip bumps.

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SiGe Surface Changes During Dry Cleaning with NF3 / H2O Plasma (NF3 / H2O 원거리 플라즈마 건식 세정에 의한 SiGe 표면 특성 변화)

  • Park, Seran;Oh, Hoon-Jung;Kim, Kyu-Dong;Ko, Dae-Hong
    • Journal of the Semiconductor & Display Technology
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    • v.19 no.2
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    • pp.45-50
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    • 2020
  • We investigated the Si1-xGex surface properties when dry cleaning the films using NF3 / H2O remote plasma. After the dry cleaning process, it was found that about 80-250 nm wide bumps were formed on the SiGe surface regardless of Ge concentration in the rage of x = 0.1 ~ 0.3. In addition, effects of the dry cleaning processing parameters such as pressure, substrate temperature, and H2O flow rates were examined. It was found that the surface bump is significantly dependent on the flow rate of H2O. Based on these observations, we would like to provide additional guidelines for implementing the dry cleaning process to SiGe materials.

Realistic Rendering of Woven Surface using Procedural Bump Mapping (절차적 범프 매핑을 이용한 직물표면의 사실적 렌더링)

  • Kang, Young-Min
    • Journal of Korea Game Society
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    • v.10 no.3
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    • pp.103-111
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    • 2010
  • In this paper, an procedural approach to photorealistic rendering of woven fabric material is proposed. Previously proposed procedural approaches to fabric rendering have the disadvantage that the rendering result is not sufficiently realistic. In order to enhance the realism, researchers employed example-based approaches. However, those methods have serious disadvantage that they require huge amount of storage for the various reflectance properties of diverse materials. The proposed method can express the reflectance on weft and warp yarns by alternating the anisotropic reflectance on yarns. In addition, we propose the proposed method procedurally models the bumpy yarn structure of woven fabric to obtain plausible rendering results. The proposed method can efficiently reproduce realistic virtual fabric without any reflectance data sets.

Investigating the accretion disk properties of young radio galaxies using the narrow-emission line diagnostics

  • Son, Dong-Hoon;Woo, Jong-Hak;Bennert, Vardha N.;Fu, Hai;Nagao, Tohru;Kawakatu, Nozomu;Kim, Sang-Chul
    • The Bulletin of The Korean Astronomical Society
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    • v.36 no.1
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    • pp.49.2-49.2
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    • 2011
  • To investigate whether radio galaxies have systematically different accretion disk compared to radio-quiet AGN, we obtained high quality optical spectra for a sample of 22 young radio galaxies, using the KAST Double Spectrograph at the Lick 3-m telescope. Young radio galaxies are particularly useful since the age of the radio phenomena is comparable to that of accretion disk. Based on the optical emission-line diagnostics of narrow line region, which is thought to be photoionized by the nuclear radiation, we constrain the states of the accretion disk. In addition to strong emission lines, i.e., [O I], [O II], [O III], and [Ne III], we use the [Ar III] line to break the degeneracy between the ionization parameter and the SED shape. We find that young radio galaxies show systematically different emission line ratios compared to radio-quiet Type II AGN, suggesting that young radio galaxies probably have the power-law SED without a strong big blue bump. We will present the main results of the emission-line diagnostics.

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Fabrication and Challenges of Cu-to-Cu Wafer Bonding

  • Kang, Sung-Geun;Lee, Ji-Eun;Kim, Eun-Sol;Lim, Na-Eun;Kim, Soo-Hyung;Kim, Sung-Dong;Kim, Sarah Eun-Kyung
    • Journal of the Microelectronics and Packaging Society
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    • v.19 no.2
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    • pp.29-33
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    • 2012
  • The demand for 3D wafer level integration has been increasing significantly. Although many technical challenges of wafer stacking are still remaining, wafer stacking is a key technology for 3D integration due to a high volume manufacturing, smaller package size, low cost, and no need for known good die. Among several new process techniques Cu-to-Cu wafer bonding is the key process to be optimized for the high density and high performance IC manufacturing. In this study two main challenges for Cu-to-Cu wafer bonding were evaluated: misalignment and bond quality of bonded wafers. It is demonstrated that the misalignment in a bonded wafer was mainly due to a physical movement of spacer removal step and the bond quality was significantly dependent on Cu bump dishing and oxide erosion by Cu CMP.

Full-Envelope Controller Switching Scheme Using Bumpless Transfer Implementation Algorithm (무충돌 전환 구현 알고리즘을 사용한 전비행영역 제어기 교체법)

  • Kim, Tae-Shin;Kwon, Oh-Kyu
    • Journal of the Korean Society for Aeronautical & Space Sciences
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    • v.36 no.6
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    • pp.574-580
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    • 2008
  • This paper has proposed a controller switching scheme for full-envelope aircraft control using the bumpless transfer implementation algorithm developed recently. This switching scheme has combined by proper rules the common existing method which switches the controller according to attitude and mach number of the aircraft with an optimization method which uses the cost function relating to bump phenomenon by means of controller switching criterion. This paper exemplifies the control performance improvement via simulations applied to a high performance aircraft benchmark problem in a wide operating range to test the proposed controller switching scheme.

Virtual Engraving and Frottage Simulation with Haptic Feedback (촉감을 이용한 판화와 탁본 기법의 가상 시뮬레이션)

  • Lee, Dong-Wook;Park, Ye-Seul;Park, Jin-Ah
    • Proceedings of the Korean Information Science Society Conference
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    • 2007.10b
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    • pp.206-211
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    • 2007
  • 현대 그래픽스 장치의 발전은 수년전까지 Pre-Rendered 방식을 사용해서 볼 수 있었던 영상들을 Real-Time Rendering을 통해 실시간으로 인터렉티브하게 제공하고 있다. 이러한 장치의 발전은 게임, 시뮬레이션, 미디어 아트 등의 많은 분야에서 변화를 불러 일으켰으며, 앞으로도 많은 변화를 촉진시킬 것이다. 이러한 변화 중 하나로 기존까지 실시간으로 영상을 생성하기 힘들었던 분야 중의 하나인 미술 기법들의 실시간 재생이 가능해졌다. 본 논문은 미술 기법 중 판화기법과 탁본기법을 가상의 환경에서 모사할 수 있는 어플리케이션인 Virtual Engraving과 Virtual Frottage를 제안한다. Virtual Engraving은 3차원 공간상의 가상의 물체에 대해 3차원 입출력장치와 Bump Mapping을 이용하여 조각행위에 대한 경험을 사용자에게 제공하며, Virtual Frottage는 탁본의 대상을 영상으로 받아들여 영상 처리 기법과 Pixel Shader를 통한 렌더링을 통하여 사용자에게 흥미로운 프로타주 기법의 경험을 제공한다. 두 어플리케이션 모두 시각적인 정보를 통해 사용자에게 미술 기법의 경험을 제공하며, Virtual Engraving의 경우 3차원 입출력장치를 통해 촉각적인 정보를 제공하였고 Virtual Frottage 역시 촉각 피드백을 제공할 수 있도록 연구 중이다. 이러한 미술 기법의 모사 연구는 사용자에게 보다 더 실감적인 경험뿐만 아니라 실 공간에서는 가능하지 않은 여러 효과를 제공할 수 있다.

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Driving Dynamic Characteristics of Tractor-Trailer Type Transporter for Large Scale Precision Equipment (대형 정밀장비 탑재용 트랙터-트레일러형 차량의 주행 동특성)

  • Ha, Taewan;Oh, Sanghoon
    • Journal of the Korea Institute of Military Science and Technology
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    • v.22 no.5
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    • pp.687-696
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    • 2019
  • To identify the driving dynamic characteristics of the Tractor-Trailer Type Transporter for mounting a large scale precision equipment, real vehicle driving tests on the 3 inch-bump-space-road were performed. And using general Dynamics Analysis Program - RecurDyn(V8R5), Dynamics M&S were carried out assuming the similar condition with real tests. Then the acceleration data obtained from real tests and M&S were analyzed and compared with each other in the part of root-mean-square-acceleration($g_{rms}$), peak-acceleration($g_{peak}$) and frequencies. In simple view of the $g_{rms}$ & $g_{peak}$, although the results of MRBD are more similar to ones of the real vehicle driving tests, but the results of RFlex have more information to get various useful dynamic characteristics.