Fabrication and Challenges of Cu-to-Cu Wafer Bonding |
Kang, Sung-Geun
(Microsystem Packaging Center, Seoul Technopark)
Lee, Ji-Eun (Department of Mechanical System Design Engineering, Seoul National University of Science and Technology) Kim, Eun-Sol (Department of Mechanical System Design Engineering, Seoul National University of Science and Technology) Lim, Na-Eun (Department of Mechanical System Design Engineering, Seoul National University of Science and Technology) Kim, Soo-Hyung (Microsystem Packaging Center, Seoul Technopark) Kim, Sung-Dong (Department of Mechanical System Design Engineering, Seoul National University of Science and Technology) Kim, Sarah Eun-Kyung (Graduate School of NID Fusion Technology, Seoul National University of Science and Technology) |
1 | W. Ruythooren, A. Beltran and R. Labie, "Cu-Cu Bonding Alternative to Solder based Micro-Bumping", Proc. 9th Electronics Packaging Technology Conference(EPTC), Singapore, 315, IEEE (2007). |
2 | L. Peng, H. Y. Li, D. F. Lim, G. Q. Lo, D. L. Kwong and C. S. Tan, "Fabrication and characterization of bump-less Cu-Cu bonding by wafer-on-wafer stacking for 3D IC", Proc. 12th Electronics Packaging Technology Conference(EPTC), Singapore, 787, IEEE (2010). |
3 | C. S. Tan and R. Reif, "Multi-layer silicon layer stacking based on copper wafer bonding", Electrochemical and solidstate letters, 8(6), 147 (2005). DOI ScienceOn |
4 | Y-S Tang, Y-J Chang and K-N Chen, "Wafer-level Cu-Cu bonding technology", Microelectronics Reliability, 52(2), 312 (2012). DOI ScienceOn |
5 | H. W. Zeij and P.M. Sarro, "Alignment and Overlay Characterization for 3D Integration and Advanced Packaging", Proc. 11th Electronics Packaging Technology Conference (EPTC), 447, IEEE (2009). |
6 | J-W Kim, M-H Jeong, E-J Jang and Y-B Park, "Effect of HF/ H2SO4 Pretreatment on Interfacial Adhesion Energy of Cu-Cu Direct Bonds", Microelectronic Engineering, 89, 42 (2012). DOI |
7 | J-W Kim, K-S Kim, H-J Lee, H-Y Kim, Y-B Park and S. M. Hyun, "Characterization and observation of Cu-Cu Thermo- Compression Bonding using 4-point bending test system", J. Microelectron. Packag. Soc., 18(4), 11 (2011). 과학기술학회마을 |
8 | J. Balachandran, S. Brebels, G. Carchon, M. Kuijk, W. De Raedt, B. Nauwelaers and E. Beyne, "Wafer-Level Package Interconnect Options", VLSI, 14(6), 654 (2006). |
9 | R. S. List, C. Webb and S. E. Kim, "3D Wafer Stacking Technology", Proc. 19th Adv. Metallization Conference (AMC), 29 (2002). |
10 | P. Morrow, M. Kobrinsky, M. Harmes, C. Park, S. Ramanathan, V. Ramachandrarao, H. Mog Park, G. Kloster, S. List and S. Kim, "Wafer-Level 3D Interconnects Via Cu Bonding", Proc. 21st Adv. Metallization Conference (AMC), San Diego, 125 (2004). |
11 | M. Koyanagi, "3D LSI Technology and Wafer-level Stack", Proc. 2nd International Symposium on Microelectronics and Packaging (ISMP), Seoul, 103, The Korean Microelectronics and Packaging Society, (2003). |
12 | P. R. Morrow, C. M. Park, S. Ramanathan, M. J. Kobrinsky and M. Harmes, "Three-Dimensional Wafer Stacking Via Cu-Cu Bonding Integrated With 65-nm Strained-Si/Low-k CMOS Technology", IEEE Electron Device Letters, 27(5), 335 (2006). DOI |
13 | Y. Kim, S-K Kang, S. D. Kim and S. E. Kim, "Wafer warpage analysis of stacked wafers for 3D integration", Microelectronic Engineering, 89, 46 (2012). DOI ScienceOn |
14 | Y. Kim, S. K. Kang and E. K. Kim, "Study of Thinned Si Wafer Warpage in 3D Stacked Wafers", Microelectronics Reliability, 50, 1988 (2010). DOI |
![]() |