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http://dx.doi.org/10.6117/kmeps.2012.19.2.029

Fabrication and Challenges of Cu-to-Cu Wafer Bonding  

Kang, Sung-Geun (Microsystem Packaging Center, Seoul Technopark)
Lee, Ji-Eun (Department of Mechanical System Design Engineering, Seoul National University of Science and Technology)
Kim, Eun-Sol (Department of Mechanical System Design Engineering, Seoul National University of Science and Technology)
Lim, Na-Eun (Department of Mechanical System Design Engineering, Seoul National University of Science and Technology)
Kim, Soo-Hyung (Microsystem Packaging Center, Seoul Technopark)
Kim, Sung-Dong (Department of Mechanical System Design Engineering, Seoul National University of Science and Technology)
Kim, Sarah Eun-Kyung (Graduate School of NID Fusion Technology, Seoul National University of Science and Technology)
Publication Information
Journal of the Microelectronics and Packaging Society / v.19, no.2, 2012 , pp. 29-33 More about this Journal
Abstract
The demand for 3D wafer level integration has been increasing significantly. Although many technical challenges of wafer stacking are still remaining, wafer stacking is a key technology for 3D integration due to a high volume manufacturing, smaller package size, low cost, and no need for known good die. Among several new process techniques Cu-to-Cu wafer bonding is the key process to be optimized for the high density and high performance IC manufacturing. In this study two main challenges for Cu-to-Cu wafer bonding were evaluated: misalignment and bond quality of bonded wafers. It is demonstrated that the misalignment in a bonded wafer was mainly due to a physical movement of spacer removal step and the bond quality was significantly dependent on Cu bump dishing and oxide erosion by Cu CMP.
Keywords
Wafer bonding; Misalignment; Cu bonding; CMP;
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
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