• Title/Summary/Keyword: blocking oxide

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Determination of Memory Trap Distribution in Charge Trap Type SONOSFET NVSM Cells Using Single Junction Charge Pumping Method (Single Junction Charge Pumping 방법을 이용한 전하 트랩형 SONOSFET NVSM 셀의 기억 트랩분포 결정)

  • 양전우;홍순혁;서광열
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.13 no.10
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    • pp.822-827
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    • 2000
  • The Si-SiO$_2$interface trap and nitride bulk trap distribution of SONOSFET(polysilicon-oxide-nitride-oxide-semiconductor field effect transistor) NVSM (nonvolatile semiconductor memory) cell is investigated by single junction charge pumping method. The device was fabricated by 0.35㎛ standard logic fabrication process including the ONO stack dielectrics. The thickness of ONO dielectricis are 24$\AA$ for tunnel oxide, 74 $\AA$ for nitride and 25 $\AA$ for blocking oxide, respectively. By the use of single junction charge pumping method, the lateral profiles of both interface and memory traps can be calculated directly from experimental charge pumping results without complex numerical simulation. The interface traps were almost uniformly distributed over the whole channel region and its maximum value was 7.97$\times$10$\^$10/㎠. The memory traps were uniformly distributed in the nitride layer and its maximum value was 1.04$\times$10$\^$19/㎤. The degradation characteristics of SONOSFET with write/erase cycling also were investigated.

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The Blocking Effect of Sunscreen Materials on Blue Light (자외선 차단제의 블루라이트 차단효과에 관한 연구)

  • Chung, Sang Uk;Lee, Si Eun;Choi, Sun Young;Moon, Kwon Ki;Lim, Sora;Kim, Hae Kyoung;Park, Jong Ho
    • Journal of the Society of Cosmetic Scientists of Korea
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    • v.44 no.2
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    • pp.183-189
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    • 2018
  • Blue light is the highest energy wavelengths in the visible light region and induces skin aging and active oxygen. Studies on harmful mechanism of skin are under way. Research on blue light blocking materials in cosmetics and formulation studies are in the early stage, and the test methods related to blue light blocking measurement are not established. The blue light blocking efficacy was established by referring to the test method of the sunscreen in vitro test(COLIPA guideline, ISO 24443, FDA Final Rule on Sunscreen Testing and Labeling). The blue light blocking effect was evaluated for 17 kinds out of 27 kinds of sunscreen raw materials suggested in KFDA guideline. The Effect was 14.97% for zinc oxide and 16.32% for bishexyloxyphenol methoxyphenyl triazine, 35.47% for methylene bis-benzotriazolyltetramethylbutylphenol, and 65.96% for titanium dioxide. In addition, the effect of micro-titanium dioxide was twice as high as that of the nano-titanium dioxide. The results suggested that the light blocking effect test method can be used to search for blue light blocking materials and study cosmetic formulations.

Performance Comparison of Vertical DMOSFETs in Ga2O3 and 4H-SiC (Ga2O3와 4H-SiC Vertical DMOSFET 성능 비교)

  • Chung, Eui Suk;Kim, Young Jae;Koo, Sang-Mo
    • Journal of IKEEE
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    • v.22 no.1
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    • pp.180-184
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    • 2018
  • Gallium oxide ($Ga_2O_3$) and silicon carbide (SiC) are the material with the wide band gap ($Ga_2O_3-4.8{\sim}4.9eV$, SiC-3.3 eV). These electronic properties allow high blocking voltage. In this work, we investigated the characteristic of $Ga_2O_3$ and 4H-SiC vertical depletion-mode metal-oxide-semiconductor field-effect transistors. We demonstrated that the blocking voltage and on-resistance of vertical DMOSFET is dependent with structure. The structure of $Ga_2O_3$ and 4H-SiC vertical DMOSFET was designed by using a 2-dimensional device simulation (ATLAS, Silvaco Inc.). As a result, 4H-SiC and $Ga_2O_3$ vertical DMOSFET have similar blocking voltage ($Ga_2O_3-1380V$, SiC-1420 V) and then when gate voltage is low, $Ga_2O_3-DMOSFET$ has lower on-resistance than 4H-SiC-DMOSFET, however, when gate voltage is high, 4H-SiC-DMOSFET has lower on-resistance than $Ga_2O_3-DMOSFET$. Therefore, we concluded that the material of power device should be considered by the gate voltage.

Improvement in Electrical Stability of poly-Si TFT Employing Vertical a-Si Offsets

  • Park, J.W.;Park, K.C.;Han, M.K.
    • 한국정보디스플레이학회:학술대회논문집
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    • 2000.01a
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    • pp.67-68
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    • 2000
  • Polycrystalline silicon (poly-Si) thin film transistors (TFT's) employing vertical amorphous silicon (a-Si) offsets have been fabricated without additional photolithography processes. The a-Si offset has been formed utilizing the poly-Si grain growth blocking effect by thin native oxide film during the excimer laser recrystallization of a-Si. The ON current degradation of the new device after 4 hour's electrical stress was reduced by 5 times compared with conventional poly-Si TFT's.

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Physical Characteristics of Cement Mortar Prepared Using Waste Glass and Graphene Oxide (폐유리와 산화 그래핀을 사용한 시멘트 모르타르의 물성 연구)

  • Kim, Kyoungseok;Chu, Yongsik
    • Resources Recycling
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    • v.28 no.6
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    • pp.54-63
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    • 2019
  • This study investigated on the compressive strength and the length change test with using the waste glass and graphene oxide for recycling the waste glass as the aggregate. Curing on 3-day and 7-day, the compressive strength was enhanced as the usage of waste glass was increased. Especially, the huge difference in the compressive strength was observed when the amount of substituting on the waste glass was used on 10~50%. With 50% of waste glass condition, the compressive strength was portionally enhanced as the usage of graphene oxide was increased and its value was 42.6 N/㎟ with 0.2% of graphene oxide. In terms of the length change test, the use of high content of waste glass led length change value to increase, but it was dropped down as the portion of waste glass was above 50%. Furthermore, in the case of using 50% of waste glass, the use of high amount of graphene oxide tended to decrease the length change value. That is, graphene oxide may contribute on boosting the cement hydration reaction and blocking the ion's movement.

Analysis of Nitride traps in MONOS Flash Memory (MONOS 플래시 메모리의 Nitride 트랩 분석)

  • Yang, Seung-Dong;Yun, Ho-Jin;Kim, Yu-mi;Kim, Jin-Seob;Eom, Ki-Yun;Chea, Seong-Won;Lee, Hi-Deok;Lee, Ga-Won
    • Journal of the Institute of Electronics and Information Engineers
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    • v.52 no.8
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    • pp.59-63
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    • 2015
  • This paper discusses the capacitance-voltage method in Metal-Oxide-Nitride-Oxide-Silicon (MONOS) devices to analyzed the characteristics of the top oxide/nitride, nitride/bottom oxide interface trap distribution. In the CV method, nitride trap density can be calculated based on the program characteristics of the nitride thickness variations. By applying this method, silicon rich nitride device found to have a larger trap density than stoichiometric nitride device. This result is consistent with previous studies. If this comparison analysis can be expected to result in improved reliability of the SONOS flash memory.

Nuruk Extract Inhibits Lipopolysaccharide-Induced Production of Nitrite and Interleukin-6 in RAW 264.7 Cells Through Blocking Activation of p38 Mitogen-Activated Protein Kinase

  • Kim, Jong-Eun;Jung, Sung-Keun;Lee, Sang-Jin;Lee, Ki-Won;Kim, Gye-Won;Lee, Hyong-Joo
    • Journal of Microbiology and Biotechnology
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    • v.18 no.8
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    • pp.1423-1426
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    • 2008
  • Nuruk, which is a natural inoculator and source of amylolytic enzymes, is used in Korean traditional rice wine. A methanol extract of nuruk (NE) attenuated lipopolysaccharide (LPS)-induced nitrite and interleukin (IL)-6 in RAW 264.7 cells. Both the n-hexane and water fractions from NE (MEH and MW, respectively) inhibited the production of nitrite and IL-6 in RAW 264.7 cells. MEH and MW also inhibited the LPS-induced inducible nitric oxide synthase expression. Further, and MEH protected against the LPS-induced activation of p38 mitogen-activated protein kinase. Together, these results indicate that nuruk may contribute to the anti-inflammatory and cancer-preventive effects of Korean traditional rice wine.

A study on the High Integrated 1TC SONOS Flash Memory (고집적화된 1TC SONOS 플래시 메모리에 관한 연구)

  • 김주연;이상배;한태현;안호명;서광열
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2002.07a
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    • pp.26-31
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    • 2002
  • To realize a high integrated Flash memory utilizing SONOS memory devices, the NOR type 1TC(one Transistor Cell) SONOS Flash arrays are fabricated and characterized. This SONOS Flash arrays with common source lines are designed and fabricated by conventional 0.35$\mu\textrm{m}$ CMOS process. The thickness of ONO for memory cell is tunnel oxide of 34${\AA}$, nitride of 73${\AA}$ and blocking oxide of 34${\AA}$. To investigate operating characteristics, CHEI(Channel Hot Electron Injection) method and Bit line erase method are selected as the write operation and the erase method, respectively. The disturbance characteristics according to the write/erase/read cycling are also examined. The degradation characteristics are investigated and then the reliability of SONOS flash memory is guaranteed.

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A Novel Process for Fabricating High Density Trench MOSFETs for DC-DC Converters

  • Kim, Jong-Dae;Roh, Tae-Moon;Kim, Sang-Gi;Park, Il-Yong;Yang, Yil-Sulk;Lee, Dae-Woo;Koo, Jin-Gun;Cho, Kyoung-Ik;Kang, Young-Il
    • ETRI Journal
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    • v.24 no.5
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    • pp.333-340
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    • 2002
  • We propose a new process technique for fabricating very high-density trench MOSFETs using 3 mask layers with oxide spacers and a self-aligned technique. This technique reduces the device size in trench width, source, and p-body region with a resulting increase in cell density and current driving capability as well as cost-effective production capability. We were able to obtain a higher breakdown voltage with uniform oxide grown along the trench surface. The channel density of the trench DMOSFET with a cell pitch of 2.3-2.4 ${\mu}m$ was 100 Mcell/$in^2$ and a specific on-resistance of 0.41 $m{\Omega}{\cdot}cm^2$ was obtained under a blocking voltage of 43 V.

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Design and Fabrication of a Surge Protective Device for Electrical Mains on Shipboard (전원회로용 서지방호장치의 설계 및 제작)

  • Moon, Seung-Bo;Park, Dae-Won;Song, Jae-Yong;Kil, Gyung-Suk
    • Proceedings of the Korean Society of Marine Engineers Conference
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    • 2005.06a
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    • pp.1035-1040
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    • 2005
  • This paper deals with the design rule and performance results of the surge protective devices (SPDs) for low-voltage mains on shipboard. The proposed SPDs consists of a metal oxide varistors (MOV) and a L-C filter to improve noise-elimination performance. Three kinds of SPDs are fabricated and tested by using a combination surge generator which produce the standard impulse current of 8/20${\mu}s$ 2.1kA. As a results, the proposed SPDs with series L-C filter have more excellent transient blocking and noise reduction performance than the conventional ones.

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